1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copied from the kernel sources: 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima 6*4882a593Smuzhiyun * Copyright (C) 2002 Paul Mundt 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __TOOLS_LINUX_ASM_SH_BARRIER_H 9*4882a593Smuzhiyun #define __TOOLS_LINUX_ASM_SH_BARRIER_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * A brief note on ctrl_barrier(), the control register write barrier. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * Legacy SH cores typically require a sequence of 8 nops after 15*4882a593Smuzhiyun * modification of a control register in order for the changes to take 16*4882a593Smuzhiyun * effect. On newer cores (like the sh4a and sh5) this is accomplished 17*4882a593Smuzhiyun * with icbi. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * Also note that on sh4a in the icbi case we can forego a synco for the 20*4882a593Smuzhiyun * write barrier, as it's not necessary for control registers. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Historically we have only done this type of barrier for the MMUCR, but 23*4882a593Smuzhiyun * it's also necessary for the CCR, so we make it generic here instead. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #if defined(__SH4A__) 26*4882a593Smuzhiyun #define mb() __asm__ __volatile__ ("synco": : :"memory") 27*4882a593Smuzhiyun #define rmb() mb() 28*4882a593Smuzhiyun #define wmb() mb() 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #include <asm-generic/barrier.h> 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* __TOOLS_LINUX_ASM_SH_BARRIER_H */ 34