1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Xilinx ASoC I2S audio support
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2018 Xilinx, Inc.
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun // Author: Praveen Vuppala <praveenv@xilinx.com>
8*4882a593Smuzhiyun // Author: Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <sound/pcm_params.h>
16*4882a593Smuzhiyun #include <sound/soc.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define DRV_NAME "xlnx_i2s"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define I2S_CORE_CTRL_OFFSET 0x08
21*4882a593Smuzhiyun #define I2S_I2STIM_OFFSET 0x20
22*4882a593Smuzhiyun #define I2S_CH0_OFFSET 0x30
23*4882a593Smuzhiyun #define I2S_I2STIM_VALID_MASK GENMASK(7, 0)
24*4882a593Smuzhiyun
xlnx_i2s_set_sclkout_div(struct snd_soc_dai * cpu_dai,int div_id,int div)25*4882a593Smuzhiyun static int xlnx_i2s_set_sclkout_div(struct snd_soc_dai *cpu_dai,
26*4882a593Smuzhiyun int div_id, int div)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun void __iomem *base = snd_soc_dai_get_drvdata(cpu_dai);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun if (!div || (div & ~I2S_I2STIM_VALID_MASK))
31*4882a593Smuzhiyun return -EINVAL;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun writel(div, base + I2S_I2STIM_OFFSET);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return 0;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
xlnx_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * i2s_dai)38*4882a593Smuzhiyun static int xlnx_i2s_hw_params(struct snd_pcm_substream *substream,
39*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
40*4882a593Smuzhiyun struct snd_soc_dai *i2s_dai)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun u32 reg_off, chan_id;
43*4882a593Smuzhiyun void __iomem *base = snd_soc_dai_get_drvdata(i2s_dai);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun chan_id = params_channels(params) / 2;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun while (chan_id > 0) {
48*4882a593Smuzhiyun reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4);
49*4882a593Smuzhiyun writel(chan_id, base + reg_off);
50*4882a593Smuzhiyun chan_id--;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
xlnx_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * i2s_dai)56*4882a593Smuzhiyun static int xlnx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
57*4882a593Smuzhiyun struct snd_soc_dai *i2s_dai)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun void __iomem *base = snd_soc_dai_get_drvdata(i2s_dai);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun switch (cmd) {
62*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
63*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
64*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
65*4882a593Smuzhiyun writel(1, base + I2S_CORE_CTRL_OFFSET);
66*4882a593Smuzhiyun break;
67*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
68*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
69*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
70*4882a593Smuzhiyun writel(0, base + I2S_CORE_CTRL_OFFSET);
71*4882a593Smuzhiyun break;
72*4882a593Smuzhiyun default:
73*4882a593Smuzhiyun return -EINVAL;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const struct snd_soc_dai_ops xlnx_i2s_dai_ops = {
80*4882a593Smuzhiyun .trigger = xlnx_i2s_trigger,
81*4882a593Smuzhiyun .set_clkdiv = xlnx_i2s_set_sclkout_div,
82*4882a593Smuzhiyun .hw_params = xlnx_i2s_hw_params
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static const struct snd_soc_component_driver xlnx_i2s_component = {
86*4882a593Smuzhiyun .name = DRV_NAME,
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static const struct of_device_id xlnx_i2s_of_match[] = {
90*4882a593Smuzhiyun { .compatible = "xlnx,i2s-transmitter-1.0", },
91*4882a593Smuzhiyun { .compatible = "xlnx,i2s-receiver-1.0", },
92*4882a593Smuzhiyun {},
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, xlnx_i2s_of_match);
95*4882a593Smuzhiyun
xlnx_i2s_probe(struct platform_device * pdev)96*4882a593Smuzhiyun static int xlnx_i2s_probe(struct platform_device *pdev)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun void __iomem *base;
99*4882a593Smuzhiyun struct snd_soc_dai_driver *dai_drv;
100*4882a593Smuzhiyun int ret;
101*4882a593Smuzhiyun u32 ch, format, data_width;
102*4882a593Smuzhiyun struct device *dev = &pdev->dev;
103*4882a593Smuzhiyun struct device_node *node = dev->of_node;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun dai_drv = devm_kzalloc(&pdev->dev, sizeof(*dai_drv), GFP_KERNEL);
106*4882a593Smuzhiyun if (!dai_drv)
107*4882a593Smuzhiyun return -ENOMEM;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun base = devm_platform_ioremap_resource(pdev, 0);
110*4882a593Smuzhiyun if (IS_ERR(base))
111*4882a593Smuzhiyun return PTR_ERR(base);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun ret = of_property_read_u32(node, "xlnx,num-channels", &ch);
114*4882a593Smuzhiyun if (ret < 0) {
115*4882a593Smuzhiyun dev_err(dev, "cannot get supported channels\n");
116*4882a593Smuzhiyun return ret;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun ch = ch * 2;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun ret = of_property_read_u32(node, "xlnx,dwidth", &data_width);
121*4882a593Smuzhiyun if (ret < 0) {
122*4882a593Smuzhiyun dev_err(dev, "cannot get data width\n");
123*4882a593Smuzhiyun return ret;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun switch (data_width) {
126*4882a593Smuzhiyun case 16:
127*4882a593Smuzhiyun format = SNDRV_PCM_FMTBIT_S16_LE;
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun case 24:
130*4882a593Smuzhiyun format = SNDRV_PCM_FMTBIT_S24_LE;
131*4882a593Smuzhiyun break;
132*4882a593Smuzhiyun default:
133*4882a593Smuzhiyun return -EINVAL;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun if (of_device_is_compatible(node, "xlnx,i2s-transmitter-1.0")) {
137*4882a593Smuzhiyun dai_drv->name = "xlnx_i2s_playback";
138*4882a593Smuzhiyun dai_drv->playback.stream_name = "Playback";
139*4882a593Smuzhiyun dai_drv->playback.formats = format;
140*4882a593Smuzhiyun dai_drv->playback.channels_min = ch;
141*4882a593Smuzhiyun dai_drv->playback.channels_max = ch;
142*4882a593Smuzhiyun dai_drv->playback.rates = SNDRV_PCM_RATE_8000_192000;
143*4882a593Smuzhiyun dai_drv->ops = &xlnx_i2s_dai_ops;
144*4882a593Smuzhiyun } else if (of_device_is_compatible(node, "xlnx,i2s-receiver-1.0")) {
145*4882a593Smuzhiyun dai_drv->name = "xlnx_i2s_capture";
146*4882a593Smuzhiyun dai_drv->capture.stream_name = "Capture";
147*4882a593Smuzhiyun dai_drv->capture.formats = format;
148*4882a593Smuzhiyun dai_drv->capture.channels_min = ch;
149*4882a593Smuzhiyun dai_drv->capture.channels_max = ch;
150*4882a593Smuzhiyun dai_drv->capture.rates = SNDRV_PCM_RATE_8000_192000;
151*4882a593Smuzhiyun dai_drv->ops = &xlnx_i2s_dai_ops;
152*4882a593Smuzhiyun } else {
153*4882a593Smuzhiyun return -ENODEV;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun dev_set_drvdata(&pdev->dev, base);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&pdev->dev, &xlnx_i2s_component,
159*4882a593Smuzhiyun dai_drv, 1);
160*4882a593Smuzhiyun if (ret) {
161*4882a593Smuzhiyun dev_err(&pdev->dev, "i2s component registration failed\n");
162*4882a593Smuzhiyun return ret;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun dev_info(&pdev->dev, "%s DAI registered\n", dai_drv->name);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun return ret;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static struct platform_driver xlnx_i2s_aud_driver = {
171*4882a593Smuzhiyun .driver = {
172*4882a593Smuzhiyun .name = DRV_NAME,
173*4882a593Smuzhiyun .of_match_table = xlnx_i2s_of_match,
174*4882a593Smuzhiyun },
175*4882a593Smuzhiyun .probe = xlnx_i2s_probe,
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun module_platform_driver(xlnx_i2s_aud_driver);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
181*4882a593Smuzhiyun MODULE_AUTHOR("Praveen Vuppala <praveenv@xilinx.com>");
182*4882a593Smuzhiyun MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>");
183