xref: /OK3568_Linux_fs/kernel/sound/soc/ux500/ux500_pcm.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) ST-Ericsson SA 2012
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
6*4882a593Smuzhiyun  *         Roger Nilsson <roger.xr.nilsson@stericsson.com>
7*4882a593Smuzhiyun  *         for ST-Ericsson.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * License terms:
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <asm/page.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/dma-mapping.h>
16*4882a593Smuzhiyun #include <linux/dmaengine.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/platform_data/dma-ste-dma40.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <sound/pcm.h>
21*4882a593Smuzhiyun #include <sound/pcm_params.h>
22*4882a593Smuzhiyun #include <sound/soc.h>
23*4882a593Smuzhiyun #include <sound/dmaengine_pcm.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include "ux500_msp_i2s.h"
26*4882a593Smuzhiyun #include "ux500_pcm.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define UX500_PLATFORM_PERIODS_BYTES_MIN	128
29*4882a593Smuzhiyun #define UX500_PLATFORM_PERIODS_BYTES_MAX	(64 * PAGE_SIZE)
30*4882a593Smuzhiyun #define UX500_PLATFORM_PERIODS_MIN		2
31*4882a593Smuzhiyun #define UX500_PLATFORM_PERIODS_MAX		48
32*4882a593Smuzhiyun #define UX500_PLATFORM_BUFFER_BYTES_MAX		(2048 * PAGE_SIZE)
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static const struct snd_pcm_hardware ux500_pcm_hw = {
35*4882a593Smuzhiyun 	.info = SNDRV_PCM_INFO_INTERLEAVED |
36*4882a593Smuzhiyun 		SNDRV_PCM_INFO_MMAP |
37*4882a593Smuzhiyun 		SNDRV_PCM_INFO_RESUME |
38*4882a593Smuzhiyun 		SNDRV_PCM_INFO_PAUSE,
39*4882a593Smuzhiyun 	.buffer_bytes_max = UX500_PLATFORM_BUFFER_BYTES_MAX,
40*4882a593Smuzhiyun 	.period_bytes_min = UX500_PLATFORM_PERIODS_BYTES_MIN,
41*4882a593Smuzhiyun 	.period_bytes_max = UX500_PLATFORM_PERIODS_BYTES_MAX,
42*4882a593Smuzhiyun 	.periods_min = UX500_PLATFORM_PERIODS_MIN,
43*4882a593Smuzhiyun 	.periods_max = UX500_PLATFORM_PERIODS_MAX,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
ux500_pcm_request_chan(struct snd_soc_pcm_runtime * rtd,struct snd_pcm_substream * substream)46*4882a593Smuzhiyun static struct dma_chan *ux500_pcm_request_chan(struct snd_soc_pcm_runtime *rtd,
47*4882a593Smuzhiyun 	struct snd_pcm_substream *substream)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
50*4882a593Smuzhiyun 	u16 per_data_width, mem_data_width;
51*4882a593Smuzhiyun 	struct stedma40_chan_cfg *dma_cfg;
52*4882a593Smuzhiyun 	struct ux500_msp_dma_params *dma_params;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	dma_params = snd_soc_dai_get_dma_data(dai, substream);
55*4882a593Smuzhiyun 	dma_cfg = dma_params->dma_cfg;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	mem_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	switch (dma_params->data_size) {
60*4882a593Smuzhiyun 	case 32:
61*4882a593Smuzhiyun 		per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
62*4882a593Smuzhiyun 		break;
63*4882a593Smuzhiyun 	case 16:
64*4882a593Smuzhiyun 		per_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
65*4882a593Smuzhiyun 		break;
66*4882a593Smuzhiyun 	case 8:
67*4882a593Smuzhiyun 		per_data_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
68*4882a593Smuzhiyun 		break;
69*4882a593Smuzhiyun 	default:
70*4882a593Smuzhiyun 		per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
71*4882a593Smuzhiyun 	}
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
74*4882a593Smuzhiyun 		dma_cfg->src_info.data_width = mem_data_width;
75*4882a593Smuzhiyun 		dma_cfg->dst_info.data_width = per_data_width;
76*4882a593Smuzhiyun 	} else {
77*4882a593Smuzhiyun 		dma_cfg->src_info.data_width = per_data_width;
78*4882a593Smuzhiyun 		dma_cfg->dst_info.data_width = mem_data_width;
79*4882a593Smuzhiyun 	}
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	return snd_dmaengine_pcm_request_channel(stedma40_filter, dma_cfg);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun 
ux500_pcm_prepare_slave_config(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct dma_slave_config * slave_config)84*4882a593Smuzhiyun static int ux500_pcm_prepare_slave_config(struct snd_pcm_substream *substream,
85*4882a593Smuzhiyun 		struct snd_pcm_hw_params *params,
86*4882a593Smuzhiyun 		struct dma_slave_config *slave_config)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
89*4882a593Smuzhiyun 	struct msp_i2s_platform_data *pdata = asoc_rtd_to_cpu(rtd, 0)->dev->platform_data;
90*4882a593Smuzhiyun 	struct snd_dmaengine_dai_dma_data *snd_dma_params;
91*4882a593Smuzhiyun 	struct ux500_msp_dma_params *ste_dma_params;
92*4882a593Smuzhiyun 	dma_addr_t dma_addr;
93*4882a593Smuzhiyun 	int ret;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	if (pdata) {
96*4882a593Smuzhiyun 		ste_dma_params =
97*4882a593Smuzhiyun 			snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
98*4882a593Smuzhiyun 		dma_addr = ste_dma_params->tx_rx_addr;
99*4882a593Smuzhiyun 	} else {
100*4882a593Smuzhiyun 		snd_dma_params =
101*4882a593Smuzhiyun 			snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
102*4882a593Smuzhiyun 		dma_addr = snd_dma_params->addr;
103*4882a593Smuzhiyun 	}
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	ret = snd_hwparams_to_dma_slave_config(substream, params, slave_config);
106*4882a593Smuzhiyun 	if (ret)
107*4882a593Smuzhiyun 		return ret;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	slave_config->dst_maxburst = 4;
110*4882a593Smuzhiyun 	slave_config->src_maxburst = 4;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
113*4882a593Smuzhiyun 	slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
116*4882a593Smuzhiyun 		slave_config->dst_addr = dma_addr;
117*4882a593Smuzhiyun 	else
118*4882a593Smuzhiyun 		slave_config->src_addr = dma_addr;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun static const struct snd_dmaengine_pcm_config ux500_dmaengine_pcm_config = {
124*4882a593Smuzhiyun 	.pcm_hardware = &ux500_pcm_hw,
125*4882a593Smuzhiyun 	.compat_request_channel = ux500_pcm_request_chan,
126*4882a593Smuzhiyun 	.prealloc_buffer_size = 128 * 1024,
127*4882a593Smuzhiyun 	.prepare_slave_config = ux500_pcm_prepare_slave_config,
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun static const struct snd_dmaengine_pcm_config ux500_dmaengine_of_pcm_config = {
131*4882a593Smuzhiyun 	.compat_request_channel = ux500_pcm_request_chan,
132*4882a593Smuzhiyun 	.prepare_slave_config = ux500_pcm_prepare_slave_config,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
ux500_pcm_register_platform(struct platform_device * pdev)135*4882a593Smuzhiyun int ux500_pcm_register_platform(struct platform_device *pdev)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	const struct snd_dmaengine_pcm_config *pcm_config;
138*4882a593Smuzhiyun 	struct device_node *np = pdev->dev.of_node;
139*4882a593Smuzhiyun 	int ret;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	if (np)
142*4882a593Smuzhiyun 		pcm_config = &ux500_dmaengine_of_pcm_config;
143*4882a593Smuzhiyun 	else
144*4882a593Smuzhiyun 		pcm_config = &ux500_dmaengine_pcm_config;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	ret = snd_dmaengine_pcm_register(&pdev->dev, pcm_config,
147*4882a593Smuzhiyun 					 SND_DMAENGINE_PCM_FLAG_COMPAT);
148*4882a593Smuzhiyun 	if (ret < 0) {
149*4882a593Smuzhiyun 		dev_err(&pdev->dev,
150*4882a593Smuzhiyun 			"%s: ERROR: Failed to register platform '%s' (%d)!\n",
151*4882a593Smuzhiyun 			__func__, pdev->name, ret);
152*4882a593Smuzhiyun 		return ret;
153*4882a593Smuzhiyun 	}
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ux500_pcm_register_platform);
158*4882a593Smuzhiyun 
ux500_pcm_unregister_platform(struct platform_device * pdev)159*4882a593Smuzhiyun int ux500_pcm_unregister_platform(struct platform_device *pdev)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun 	snd_dmaengine_pcm_unregister(&pdev->dev);
162*4882a593Smuzhiyun 	return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ux500_pcm_unregister_platform);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun MODULE_AUTHOR("Ola Lilja");
167*4882a593Smuzhiyun MODULE_AUTHOR("Roger Nilsson");
168*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC UX500 driver");
169*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
170