1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) ST-Ericsson SA 2012 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 6*4882a593Smuzhiyun * Roger Nilsson <roger.xr.nilsson@stericsson.com> 7*4882a593Smuzhiyun * for ST-Ericsson. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * License terms: 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef UX500_msp_dai_H 13*4882a593Smuzhiyun #define UX500_msp_dai_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <linux/types.h> 16*4882a593Smuzhiyun #include <linux/spinlock.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include "ux500_msp_i2s.h" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define UX500_NBR_OF_DAI 4 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define UX500_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | \ 23*4882a593Smuzhiyun SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define UX500_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define FRAME_PER_SINGLE_SLOT_8_KHZ 31 28*4882a593Smuzhiyun #define FRAME_PER_SINGLE_SLOT_16_KHZ 124 29*4882a593Smuzhiyun #define FRAME_PER_SINGLE_SLOT_44_1_KHZ 63 30*4882a593Smuzhiyun #define FRAME_PER_SINGLE_SLOT_48_KHZ 49 31*4882a593Smuzhiyun #define FRAME_PER_2_SLOTS 31 32*4882a593Smuzhiyun #define FRAME_PER_8_SLOTS 138 33*4882a593Smuzhiyun #define FRAME_PER_16_SLOTS 277 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define UX500_MSP_INTERNAL_CLOCK_FREQ 40000000 36*4882a593Smuzhiyun #define UX500_MSP1_INTERNAL_CLOCK_FREQ UX500_MSP_INTERNAL_CLOCK_FREQ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define UX500_MSP_MIN_CHANNELS 1 39*4882a593Smuzhiyun #define UX500_MSP_MAX_CHANNELS 8 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define PLAYBACK_CONFIGURED 1 42*4882a593Smuzhiyun #define CAPTURE_CONFIGURED 2 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun enum ux500_msp_clock_id { 45*4882a593Smuzhiyun UX500_MSP_MASTER_CLOCK, 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct ux500_msp_i2s_drvdata { 49*4882a593Smuzhiyun struct ux500_msp *msp; 50*4882a593Smuzhiyun struct regulator *reg_vape; 51*4882a593Smuzhiyun unsigned int fmt; 52*4882a593Smuzhiyun unsigned int tx_mask; 53*4882a593Smuzhiyun unsigned int rx_mask; 54*4882a593Smuzhiyun int slots; 55*4882a593Smuzhiyun int slot_width; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Clocks */ 58*4882a593Smuzhiyun unsigned int master_clk; 59*4882a593Smuzhiyun struct clk *clk; 60*4882a593Smuzhiyun struct clk *pclk; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Regulators */ 63*4882a593Smuzhiyun int vape_opp_constraint; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun int ux500_msp_dai_set_data_delay(struct snd_soc_dai *dai, int delay); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif 69