1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * TXx9 SoC AC Link Controller 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __TXX9ACLC_H 7*4882a593Smuzhiyun #define __TXX9ACLC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/interrupt.h> 10*4882a593Smuzhiyun #include <asm/txx9/dmac.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define ACCTLEN 0x00 /* control enable */ 13*4882a593Smuzhiyun #define ACCTLDIS 0x04 /* control disable */ 14*4882a593Smuzhiyun #define ACCTL_ENLINK 0x00000001 /* enable/disable AC-link */ 15*4882a593Smuzhiyun #define ACCTL_AUDODMA 0x00000100 /* AUDODMA enable/disable */ 16*4882a593Smuzhiyun #define ACCTL_AUDIDMA 0x00001000 /* AUDIDMA enable/disable */ 17*4882a593Smuzhiyun #define ACCTL_AUDOEHLT 0x00010000 /* AUDO error halt 18*4882a593Smuzhiyun enable/disable */ 19*4882a593Smuzhiyun #define ACCTL_AUDIEHLT 0x00100000 /* AUDI error halt 20*4882a593Smuzhiyun enable/disable */ 21*4882a593Smuzhiyun #define ACREGACC 0x08 /* codec register access */ 22*4882a593Smuzhiyun #define ACREGACC_DAT_SHIFT 0 /* data field */ 23*4882a593Smuzhiyun #define ACREGACC_REG_SHIFT 16 /* address field */ 24*4882a593Smuzhiyun #define ACREGACC_CODECID_SHIFT 24 /* CODEC ID field */ 25*4882a593Smuzhiyun #define ACREGACC_READ 0x80000000 /* CODEC read */ 26*4882a593Smuzhiyun #define ACREGACC_WRITE 0x00000000 /* CODEC write */ 27*4882a593Smuzhiyun #define ACINTSTS 0x10 /* interrupt status */ 28*4882a593Smuzhiyun #define ACINTMSTS 0x14 /* interrupt masked status */ 29*4882a593Smuzhiyun #define ACINTEN 0x18 /* interrupt enable */ 30*4882a593Smuzhiyun #define ACINTDIS 0x1c /* interrupt disable */ 31*4882a593Smuzhiyun #define ACINT_CODECRDY(n) (0x00000001 << (n)) /* CODECn ready */ 32*4882a593Smuzhiyun #define ACINT_REGACCRDY 0x00000010 /* ACREGACC ready */ 33*4882a593Smuzhiyun #define ACINT_AUDOERR 0x00000100 /* AUDO underrun error */ 34*4882a593Smuzhiyun #define ACINT_AUDIERR 0x00001000 /* AUDI overrun error */ 35*4882a593Smuzhiyun #define ACDMASTS 0x80 /* DMA request status */ 36*4882a593Smuzhiyun #define ACDMA_AUDO 0x00000001 /* AUDODMA pending */ 37*4882a593Smuzhiyun #define ACDMA_AUDI 0x00000010 /* AUDIDMA pending */ 38*4882a593Smuzhiyun #define ACAUDODAT 0xa0 /* audio out data */ 39*4882a593Smuzhiyun #define ACAUDIDAT 0xb0 /* audio in data */ 40*4882a593Smuzhiyun #define ACREVID 0xfc /* revision ID */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct txx9aclc_dmadata { 43*4882a593Smuzhiyun struct resource *dma_res; 44*4882a593Smuzhiyun struct txx9dmac_slave dma_slave; 45*4882a593Smuzhiyun struct dma_chan *dma_chan; 46*4882a593Smuzhiyun struct work_struct work; 47*4882a593Smuzhiyun spinlock_t dma_lock; 48*4882a593Smuzhiyun int stream; /* SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE */ 49*4882a593Smuzhiyun struct snd_pcm_substream *substream; 50*4882a593Smuzhiyun unsigned long pos; 51*4882a593Smuzhiyun dma_addr_t dma_addr; 52*4882a593Smuzhiyun unsigned long buffer_bytes; 53*4882a593Smuzhiyun unsigned long period_bytes; 54*4882a593Smuzhiyun unsigned long frag_bytes; 55*4882a593Smuzhiyun int frags; 56*4882a593Smuzhiyun int frag_count; 57*4882a593Smuzhiyun int dmacount; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct txx9aclc_plat_drvdata { 61*4882a593Smuzhiyun void __iomem *base; 62*4882a593Smuzhiyun u64 physbase; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun txx9aclc_get_plat_drvdata(struct snd_soc_dai * dai)65*4882a593Smuzhiyunstatic inline struct txx9aclc_plat_drvdata *txx9aclc_get_plat_drvdata( 66*4882a593Smuzhiyun struct snd_soc_dai *dai) 67*4882a593Smuzhiyun { 68*4882a593Smuzhiyun return dev_get_drvdata(dai->dev); 69*4882a593Smuzhiyun } 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #endif /* __TXX9ACLC_H */ 72