1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Generic TXx9 ACLC platform driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009 Atsushi Nemoto
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on RBTX49xx patch from CELF patch archive.
8*4882a593Smuzhiyun * (C) Copyright TOSHIBA CORPORATION 2004-2006
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/scatterlist.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/dmaengine.h>
17*4882a593Smuzhiyun #include <sound/core.h>
18*4882a593Smuzhiyun #include <sound/pcm.h>
19*4882a593Smuzhiyun #include <sound/pcm_params.h>
20*4882a593Smuzhiyun #include <sound/soc.h>
21*4882a593Smuzhiyun #include "txx9aclc.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define DRV_NAME "txx9aclc"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static struct txx9aclc_soc_device {
26*4882a593Smuzhiyun struct txx9aclc_dmadata dmadata[2];
27*4882a593Smuzhiyun } txx9aclc_soc_device;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* REVISIT: How to find txx9aclc_drvdata from snd_ac97? */
30*4882a593Smuzhiyun static struct txx9aclc_plat_drvdata *txx9aclc_drvdata;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static int txx9aclc_dma_init(struct txx9aclc_soc_device *dev,
33*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static const struct snd_pcm_hardware txx9aclc_pcm_hardware = {
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun * REVISIT: SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID
38*4882a593Smuzhiyun * needs more works for noncoherent MIPS.
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun .info = SNDRV_PCM_INFO_INTERLEAVED |
41*4882a593Smuzhiyun SNDRV_PCM_INFO_BATCH |
42*4882a593Smuzhiyun SNDRV_PCM_INFO_PAUSE,
43*4882a593Smuzhiyun .period_bytes_min = 1024,
44*4882a593Smuzhiyun .period_bytes_max = 8 * 1024,
45*4882a593Smuzhiyun .periods_min = 2,
46*4882a593Smuzhiyun .periods_max = 4096,
47*4882a593Smuzhiyun .buffer_bytes_max = 32 * 1024,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
txx9aclc_pcm_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)50*4882a593Smuzhiyun static int txx9aclc_pcm_hw_params(struct snd_soc_component *component,
51*4882a593Smuzhiyun struct snd_pcm_substream *substream,
52*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
55*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata = runtime->private_data;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun dev_dbg(component->dev,
58*4882a593Smuzhiyun "runtime->dma_area = %#lx dma_addr = %#lx dma_bytes = %zd "
59*4882a593Smuzhiyun "runtime->min_align %ld\n",
60*4882a593Smuzhiyun (unsigned long)runtime->dma_area,
61*4882a593Smuzhiyun (unsigned long)runtime->dma_addr, runtime->dma_bytes,
62*4882a593Smuzhiyun runtime->min_align);
63*4882a593Smuzhiyun dev_dbg(component->dev,
64*4882a593Smuzhiyun "periods %d period_bytes %d stream %d\n",
65*4882a593Smuzhiyun params_periods(params), params_period_bytes(params),
66*4882a593Smuzhiyun substream->stream);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun dmadata->substream = substream;
69*4882a593Smuzhiyun dmadata->pos = 0;
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
txx9aclc_pcm_prepare(struct snd_soc_component * component,struct snd_pcm_substream * substream)73*4882a593Smuzhiyun static int txx9aclc_pcm_prepare(struct snd_soc_component *component,
74*4882a593Smuzhiyun struct snd_pcm_substream *substream)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
77*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata = runtime->private_data;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun dmadata->dma_addr = runtime->dma_addr;
80*4882a593Smuzhiyun dmadata->buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
81*4882a593Smuzhiyun dmadata->period_bytes = snd_pcm_lib_period_bytes(substream);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun if (dmadata->buffer_bytes == dmadata->period_bytes) {
84*4882a593Smuzhiyun dmadata->frag_bytes = dmadata->period_bytes >> 1;
85*4882a593Smuzhiyun dmadata->frags = 2;
86*4882a593Smuzhiyun } else {
87*4882a593Smuzhiyun dmadata->frag_bytes = dmadata->period_bytes;
88*4882a593Smuzhiyun dmadata->frags = dmadata->buffer_bytes / dmadata->period_bytes;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun dmadata->frag_count = 0;
91*4882a593Smuzhiyun dmadata->pos = 0;
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
txx9aclc_dma_complete(void * arg)95*4882a593Smuzhiyun static void txx9aclc_dma_complete(void *arg)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata = arg;
98*4882a593Smuzhiyun unsigned long flags;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* dma completion handler cannot submit new operations */
101*4882a593Smuzhiyun spin_lock_irqsave(&dmadata->dma_lock, flags);
102*4882a593Smuzhiyun if (dmadata->frag_count >= 0) {
103*4882a593Smuzhiyun dmadata->dmacount--;
104*4882a593Smuzhiyun if (!WARN_ON(dmadata->dmacount < 0))
105*4882a593Smuzhiyun queue_work(system_highpri_wq, &dmadata->work);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun spin_unlock_irqrestore(&dmadata->dma_lock, flags);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static struct dma_async_tx_descriptor *
txx9aclc_dma_submit(struct txx9aclc_dmadata * dmadata,dma_addr_t buf_dma_addr)111*4882a593Smuzhiyun txx9aclc_dma_submit(struct txx9aclc_dmadata *dmadata, dma_addr_t buf_dma_addr)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct dma_chan *chan = dmadata->dma_chan;
114*4882a593Smuzhiyun struct dma_async_tx_descriptor *desc;
115*4882a593Smuzhiyun struct scatterlist sg;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun sg_init_table(&sg, 1);
118*4882a593Smuzhiyun sg_set_page(&sg, pfn_to_page(PFN_DOWN(buf_dma_addr)),
119*4882a593Smuzhiyun dmadata->frag_bytes, buf_dma_addr & (PAGE_SIZE - 1));
120*4882a593Smuzhiyun sg_dma_address(&sg) = buf_dma_addr;
121*4882a593Smuzhiyun desc = dmaengine_prep_slave_sg(chan, &sg, 1,
122*4882a593Smuzhiyun dmadata->substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
123*4882a593Smuzhiyun DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
124*4882a593Smuzhiyun DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
125*4882a593Smuzhiyun if (!desc) {
126*4882a593Smuzhiyun dev_err(&chan->dev->device, "cannot prepare slave dma\n");
127*4882a593Smuzhiyun return NULL;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun desc->callback = txx9aclc_dma_complete;
130*4882a593Smuzhiyun desc->callback_param = dmadata;
131*4882a593Smuzhiyun dmaengine_submit(desc);
132*4882a593Smuzhiyun return desc;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #define NR_DMA_CHAIN 2
136*4882a593Smuzhiyun
txx9aclc_dma_work(struct work_struct * work)137*4882a593Smuzhiyun static void txx9aclc_dma_work(struct work_struct *work)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata =
140*4882a593Smuzhiyun container_of(work, struct txx9aclc_dmadata, work);
141*4882a593Smuzhiyun struct dma_chan *chan = dmadata->dma_chan;
142*4882a593Smuzhiyun struct dma_async_tx_descriptor *desc;
143*4882a593Smuzhiyun struct snd_pcm_substream *substream = dmadata->substream;
144*4882a593Smuzhiyun u32 ctlbit = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
145*4882a593Smuzhiyun ACCTL_AUDODMA : ACCTL_AUDIDMA;
146*4882a593Smuzhiyun int i;
147*4882a593Smuzhiyun unsigned long flags;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun spin_lock_irqsave(&dmadata->dma_lock, flags);
150*4882a593Smuzhiyun if (dmadata->frag_count < 0) {
151*4882a593Smuzhiyun struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
152*4882a593Smuzhiyun void __iomem *base = drvdata->base;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun spin_unlock_irqrestore(&dmadata->dma_lock, flags);
155*4882a593Smuzhiyun dmaengine_terminate_all(chan);
156*4882a593Smuzhiyun /* first time */
157*4882a593Smuzhiyun for (i = 0; i < NR_DMA_CHAIN; i++) {
158*4882a593Smuzhiyun desc = txx9aclc_dma_submit(dmadata,
159*4882a593Smuzhiyun dmadata->dma_addr + i * dmadata->frag_bytes);
160*4882a593Smuzhiyun if (!desc)
161*4882a593Smuzhiyun return;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun dmadata->dmacount = NR_DMA_CHAIN;
164*4882a593Smuzhiyun dma_async_issue_pending(chan);
165*4882a593Smuzhiyun spin_lock_irqsave(&dmadata->dma_lock, flags);
166*4882a593Smuzhiyun __raw_writel(ctlbit, base + ACCTLEN);
167*4882a593Smuzhiyun dmadata->frag_count = NR_DMA_CHAIN % dmadata->frags;
168*4882a593Smuzhiyun spin_unlock_irqrestore(&dmadata->dma_lock, flags);
169*4882a593Smuzhiyun return;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun if (WARN_ON(dmadata->dmacount >= NR_DMA_CHAIN)) {
172*4882a593Smuzhiyun spin_unlock_irqrestore(&dmadata->dma_lock, flags);
173*4882a593Smuzhiyun return;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun while (dmadata->dmacount < NR_DMA_CHAIN) {
176*4882a593Smuzhiyun dmadata->dmacount++;
177*4882a593Smuzhiyun spin_unlock_irqrestore(&dmadata->dma_lock, flags);
178*4882a593Smuzhiyun desc = txx9aclc_dma_submit(dmadata,
179*4882a593Smuzhiyun dmadata->dma_addr +
180*4882a593Smuzhiyun dmadata->frag_count * dmadata->frag_bytes);
181*4882a593Smuzhiyun if (!desc)
182*4882a593Smuzhiyun return;
183*4882a593Smuzhiyun dma_async_issue_pending(chan);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun spin_lock_irqsave(&dmadata->dma_lock, flags);
186*4882a593Smuzhiyun dmadata->frag_count++;
187*4882a593Smuzhiyun dmadata->frag_count %= dmadata->frags;
188*4882a593Smuzhiyun dmadata->pos += dmadata->frag_bytes;
189*4882a593Smuzhiyun dmadata->pos %= dmadata->buffer_bytes;
190*4882a593Smuzhiyun if ((dmadata->frag_count * dmadata->frag_bytes) %
191*4882a593Smuzhiyun dmadata->period_bytes == 0)
192*4882a593Smuzhiyun snd_pcm_period_elapsed(substream);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun spin_unlock_irqrestore(&dmadata->dma_lock, flags);
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
txx9aclc_pcm_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)197*4882a593Smuzhiyun static int txx9aclc_pcm_trigger(struct snd_soc_component *component,
198*4882a593Smuzhiyun struct snd_pcm_substream *substream, int cmd)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata = substream->runtime->private_data;
201*4882a593Smuzhiyun struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
202*4882a593Smuzhiyun void __iomem *base = drvdata->base;
203*4882a593Smuzhiyun unsigned long flags;
204*4882a593Smuzhiyun int ret = 0;
205*4882a593Smuzhiyun u32 ctlbit = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
206*4882a593Smuzhiyun ACCTL_AUDODMA : ACCTL_AUDIDMA;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun spin_lock_irqsave(&dmadata->dma_lock, flags);
209*4882a593Smuzhiyun switch (cmd) {
210*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
211*4882a593Smuzhiyun dmadata->frag_count = -1;
212*4882a593Smuzhiyun queue_work(system_highpri_wq, &dmadata->work);
213*4882a593Smuzhiyun break;
214*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
215*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
216*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
217*4882a593Smuzhiyun __raw_writel(ctlbit, base + ACCTLDIS);
218*4882a593Smuzhiyun break;
219*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
220*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
221*4882a593Smuzhiyun __raw_writel(ctlbit, base + ACCTLEN);
222*4882a593Smuzhiyun break;
223*4882a593Smuzhiyun default:
224*4882a593Smuzhiyun ret = -EINVAL;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun spin_unlock_irqrestore(&dmadata->dma_lock, flags);
227*4882a593Smuzhiyun return ret;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun static snd_pcm_uframes_t
txx9aclc_pcm_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)231*4882a593Smuzhiyun txx9aclc_pcm_pointer(struct snd_soc_component *component,
232*4882a593Smuzhiyun struct snd_pcm_substream *substream)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata = substream->runtime->private_data;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun return bytes_to_frames(substream->runtime, dmadata->pos);
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
txx9aclc_pcm_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)239*4882a593Smuzhiyun static int txx9aclc_pcm_open(struct snd_soc_component *component,
240*4882a593Smuzhiyun struct snd_pcm_substream *substream)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun struct txx9aclc_soc_device *dev = &txx9aclc_soc_device;
243*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata = &dev->dmadata[substream->stream];
244*4882a593Smuzhiyun int ret;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun ret = snd_soc_set_runtime_hwparams(substream, &txx9aclc_pcm_hardware);
247*4882a593Smuzhiyun if (ret)
248*4882a593Smuzhiyun return ret;
249*4882a593Smuzhiyun /* ensure that buffer size is a multiple of period size */
250*4882a593Smuzhiyun ret = snd_pcm_hw_constraint_integer(substream->runtime,
251*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_PERIODS);
252*4882a593Smuzhiyun if (ret < 0)
253*4882a593Smuzhiyun return ret;
254*4882a593Smuzhiyun substream->runtime->private_data = dmadata;
255*4882a593Smuzhiyun return 0;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun
txx9aclc_pcm_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)258*4882a593Smuzhiyun static int txx9aclc_pcm_close(struct snd_soc_component *component,
259*4882a593Smuzhiyun struct snd_pcm_substream *substream)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata = substream->runtime->private_data;
262*4882a593Smuzhiyun struct dma_chan *chan = dmadata->dma_chan;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun dmadata->frag_count = -1;
265*4882a593Smuzhiyun dmaengine_terminate_all(chan);
266*4882a593Smuzhiyun return 0;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
txx9aclc_pcm_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)269*4882a593Smuzhiyun static int txx9aclc_pcm_new(struct snd_soc_component *component,
270*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun struct snd_card *card = rtd->card->snd_card;
273*4882a593Smuzhiyun struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
274*4882a593Smuzhiyun struct snd_pcm *pcm = rtd->pcm;
275*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(component->dev);
276*4882a593Smuzhiyun struct txx9aclc_soc_device *dev;
277*4882a593Smuzhiyun struct resource *r;
278*4882a593Smuzhiyun int i;
279*4882a593Smuzhiyun int ret;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /* at this point onwards the AC97 component has probed and this will be valid */
282*4882a593Smuzhiyun dev = snd_soc_dai_get_drvdata(dai);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun dev->dmadata[0].stream = SNDRV_PCM_STREAM_PLAYBACK;
285*4882a593Smuzhiyun dev->dmadata[1].stream = SNDRV_PCM_STREAM_CAPTURE;
286*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
287*4882a593Smuzhiyun r = platform_get_resource(pdev, IORESOURCE_DMA, i);
288*4882a593Smuzhiyun if (!r) {
289*4882a593Smuzhiyun ret = -EBUSY;
290*4882a593Smuzhiyun goto exit;
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun dev->dmadata[i].dma_res = r;
293*4882a593Smuzhiyun ret = txx9aclc_dma_init(dev, &dev->dmadata[i]);
294*4882a593Smuzhiyun if (ret)
295*4882a593Smuzhiyun goto exit;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
299*4882a593Smuzhiyun card->dev, 64 * 1024, 4 * 1024 * 1024);
300*4882a593Smuzhiyun return 0;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun exit:
303*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
304*4882a593Smuzhiyun if (dev->dmadata[i].dma_chan)
305*4882a593Smuzhiyun dma_release_channel(dev->dmadata[i].dma_chan);
306*4882a593Smuzhiyun dev->dmadata[i].dma_chan = NULL;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun return ret;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
filter(struct dma_chan * chan,void * param)311*4882a593Smuzhiyun static bool filter(struct dma_chan *chan, void *param)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata = param;
314*4882a593Smuzhiyun char *devname;
315*4882a593Smuzhiyun bool found = false;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun devname = kasprintf(GFP_KERNEL, "%s.%d", dmadata->dma_res->name,
318*4882a593Smuzhiyun (int)dmadata->dma_res->start);
319*4882a593Smuzhiyun if (strcmp(dev_name(chan->device->dev), devname) == 0) {
320*4882a593Smuzhiyun chan->private = &dmadata->dma_slave;
321*4882a593Smuzhiyun found = true;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun kfree(devname);
324*4882a593Smuzhiyun return found;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
txx9aclc_dma_init(struct txx9aclc_soc_device * dev,struct txx9aclc_dmadata * dmadata)327*4882a593Smuzhiyun static int txx9aclc_dma_init(struct txx9aclc_soc_device *dev,
328*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
331*4882a593Smuzhiyun struct txx9dmac_slave *ds = &dmadata->dma_slave;
332*4882a593Smuzhiyun dma_cap_mask_t mask;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun spin_lock_init(&dmadata->dma_lock);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun ds->reg_width = sizeof(u32);
337*4882a593Smuzhiyun if (dmadata->stream == SNDRV_PCM_STREAM_PLAYBACK) {
338*4882a593Smuzhiyun ds->tx_reg = drvdata->physbase + ACAUDODAT;
339*4882a593Smuzhiyun ds->rx_reg = 0;
340*4882a593Smuzhiyun } else {
341*4882a593Smuzhiyun ds->tx_reg = 0;
342*4882a593Smuzhiyun ds->rx_reg = drvdata->physbase + ACAUDIDAT;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /* Try to grab a DMA channel */
346*4882a593Smuzhiyun dma_cap_zero(mask);
347*4882a593Smuzhiyun dma_cap_set(DMA_SLAVE, mask);
348*4882a593Smuzhiyun dmadata->dma_chan = dma_request_channel(mask, filter, dmadata);
349*4882a593Smuzhiyun if (!dmadata->dma_chan) {
350*4882a593Smuzhiyun printk(KERN_ERR
351*4882a593Smuzhiyun "DMA channel for %s is not available\n",
352*4882a593Smuzhiyun dmadata->stream == SNDRV_PCM_STREAM_PLAYBACK ?
353*4882a593Smuzhiyun "playback" : "capture");
354*4882a593Smuzhiyun return -EBUSY;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun INIT_WORK(&dmadata->work, txx9aclc_dma_work);
357*4882a593Smuzhiyun return 0;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
txx9aclc_pcm_probe(struct snd_soc_component * component)360*4882a593Smuzhiyun static int txx9aclc_pcm_probe(struct snd_soc_component *component)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun snd_soc_component_set_drvdata(component, &txx9aclc_soc_device);
363*4882a593Smuzhiyun return 0;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
txx9aclc_pcm_remove(struct snd_soc_component * component)366*4882a593Smuzhiyun static void txx9aclc_pcm_remove(struct snd_soc_component *component)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun struct txx9aclc_soc_device *dev = snd_soc_component_get_drvdata(component);
369*4882a593Smuzhiyun struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
370*4882a593Smuzhiyun void __iomem *base = drvdata->base;
371*4882a593Smuzhiyun int i;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun /* disable all FIFO DMAs */
374*4882a593Smuzhiyun __raw_writel(ACCTL_AUDODMA | ACCTL_AUDIDMA, base + ACCTLDIS);
375*4882a593Smuzhiyun /* dummy R/W to clear pending DMAREQ if any */
376*4882a593Smuzhiyun __raw_writel(__raw_readl(base + ACAUDIDAT), base + ACAUDODAT);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
379*4882a593Smuzhiyun struct txx9aclc_dmadata *dmadata = &dev->dmadata[i];
380*4882a593Smuzhiyun struct dma_chan *chan = dmadata->dma_chan;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun if (chan) {
383*4882a593Smuzhiyun dmadata->frag_count = -1;
384*4882a593Smuzhiyun dmaengine_terminate_all(chan);
385*4882a593Smuzhiyun dma_release_channel(chan);
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun dev->dmadata[i].dma_chan = NULL;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun static const struct snd_soc_component_driver txx9aclc_soc_component = {
392*4882a593Smuzhiyun .name = DRV_NAME,
393*4882a593Smuzhiyun .probe = txx9aclc_pcm_probe,
394*4882a593Smuzhiyun .remove = txx9aclc_pcm_remove,
395*4882a593Smuzhiyun .open = txx9aclc_pcm_open,
396*4882a593Smuzhiyun .close = txx9aclc_pcm_close,
397*4882a593Smuzhiyun .hw_params = txx9aclc_pcm_hw_params,
398*4882a593Smuzhiyun .prepare = txx9aclc_pcm_prepare,
399*4882a593Smuzhiyun .trigger = txx9aclc_pcm_trigger,
400*4882a593Smuzhiyun .pointer = txx9aclc_pcm_pointer,
401*4882a593Smuzhiyun .pcm_construct = txx9aclc_pcm_new,
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun
txx9aclc_soc_platform_probe(struct platform_device * pdev)404*4882a593Smuzhiyun static int txx9aclc_soc_platform_probe(struct platform_device *pdev)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun return devm_snd_soc_register_component(&pdev->dev,
407*4882a593Smuzhiyun &txx9aclc_soc_component, NULL, 0);
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun static struct platform_driver txx9aclc_pcm_driver = {
411*4882a593Smuzhiyun .driver = {
412*4882a593Smuzhiyun .name = "txx9aclc-pcm-audio",
413*4882a593Smuzhiyun },
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun .probe = txx9aclc_soc_platform_probe,
416*4882a593Smuzhiyun };
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun module_platform_driver(txx9aclc_pcm_driver);
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
421*4882a593Smuzhiyun MODULE_DESCRIPTION("TXx9 ACLC Audio DMA driver");
422*4882a593Smuzhiyun MODULE_LICENSE("GPL");
423