1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * omap-mcpdm.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 - 2011 Texas Instruments 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Contact: Misael Lopez Cruz <misael.lopez@ti.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __OMAP_MCPDM_H__ 11*4882a593Smuzhiyun #define __OMAP_MCPDM_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define MCPDM_REG_REVISION 0x00 14*4882a593Smuzhiyun #define MCPDM_REG_SYSCONFIG 0x10 15*4882a593Smuzhiyun #define MCPDM_REG_IRQSTATUS_RAW 0x24 16*4882a593Smuzhiyun #define MCPDM_REG_IRQSTATUS 0x28 17*4882a593Smuzhiyun #define MCPDM_REG_IRQENABLE_SET 0x2C 18*4882a593Smuzhiyun #define MCPDM_REG_IRQENABLE_CLR 0x30 19*4882a593Smuzhiyun #define MCPDM_REG_IRQWAKE_EN 0x34 20*4882a593Smuzhiyun #define MCPDM_REG_DMAENABLE_SET 0x38 21*4882a593Smuzhiyun #define MCPDM_REG_DMAENABLE_CLR 0x3C 22*4882a593Smuzhiyun #define MCPDM_REG_DMAWAKEEN 0x40 23*4882a593Smuzhiyun #define MCPDM_REG_CTRL 0x44 24*4882a593Smuzhiyun #define MCPDM_REG_DN_DATA 0x48 25*4882a593Smuzhiyun #define MCPDM_REG_UP_DATA 0x4C 26*4882a593Smuzhiyun #define MCPDM_REG_FIFO_CTRL_DN 0x50 27*4882a593Smuzhiyun #define MCPDM_REG_FIFO_CTRL_UP 0x54 28*4882a593Smuzhiyun #define MCPDM_REG_DN_OFFSET 0x58 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * MCPDM_IRQ bit fields 32*4882a593Smuzhiyun * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define MCPDM_DN_IRQ (1 << 0) 36*4882a593Smuzhiyun #define MCPDM_DN_IRQ_EMPTY (1 << 1) 37*4882a593Smuzhiyun #define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2) 38*4882a593Smuzhiyun #define MCPDM_DN_IRQ_FULL (1 << 3) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define MCPDM_UP_IRQ (1 << 8) 41*4882a593Smuzhiyun #define MCPDM_UP_IRQ_EMPTY (1 << 9) 42*4882a593Smuzhiyun #define MCPDM_UP_IRQ_ALMST_FULL (1 << 10) 43*4882a593Smuzhiyun #define MCPDM_UP_IRQ_FULL (1 << 11) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define MCPDM_DOWNLINK_IRQ_MASK 0x00F 46*4882a593Smuzhiyun #define MCPDM_UPLINK_IRQ_MASK 0xF00 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * MCPDM_DMAENABLE bit fields 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MCPDM_DMA_DN_ENABLE (1 << 0) 53*4882a593Smuzhiyun #define MCPDM_DMA_UP_ENABLE (1 << 1) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * MCPDM_CTRL bit fields 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define MCPDM_PDM_UPLINK_EN(x) (1 << (x - 1)) /* ch1 is at bit 0 */ 60*4882a593Smuzhiyun #define MCPDM_PDM_DOWNLINK_EN(x) (1 << (x + 2)) /* ch1 is at bit 3 */ 61*4882a593Smuzhiyun #define MCPDM_PDMOUTFORMAT (1 << 8) 62*4882a593Smuzhiyun #define MCPDM_CMD_INT (1 << 9) 63*4882a593Smuzhiyun #define MCPDM_STATUS_INT (1 << 10) 64*4882a593Smuzhiyun #define MCPDM_SW_UP_RST (1 << 11) 65*4882a593Smuzhiyun #define MCPDM_SW_DN_RST (1 << 12) 66*4882a593Smuzhiyun #define MCPDM_WD_EN (1 << 14) 67*4882a593Smuzhiyun #define MCPDM_PDM_UP_MASK 0x7 68*4882a593Smuzhiyun #define MCPDM_PDM_DN_MASK (0x1f << 3) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define MCPDM_PDMOUTFORMAT_LJUST (0 << 8) 72*4882a593Smuzhiyun #define MCPDM_PDMOUTFORMAT_RJUST (1 << 8) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * MCPDM_FIFO_CTRL bit fields 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define MCPDM_UP_THRES_MAX 0xF 79*4882a593Smuzhiyun #define MCPDM_DN_THRES_MAX 0xF 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* 82*4882a593Smuzhiyun * MCPDM_DN_OFFSET bit fields 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define MCPDM_DN_OFST_RX1_EN (1 << 0) 86*4882a593Smuzhiyun #define MCPDM_DNOFST_RX1(x) ((x & 0x1f) << 1) 87*4882a593Smuzhiyun #define MCPDM_DN_OFST_RX2_EN (1 << 8) 88*4882a593Smuzhiyun #define MCPDM_DNOFST_RX2(x) ((x & 0x1f) << 9) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd, 91*4882a593Smuzhiyun u8 rx1, u8 rx2); 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* End of __OMAP_MCPDM_H__ */ 94