1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * omap-dmic.h -- OMAP Digital Microphone Controller 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _OMAP_DMIC_H 7*4882a593Smuzhiyun #define _OMAP_DMIC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define OMAP_DMIC_REVISION_REG 0x00 10*4882a593Smuzhiyun #define OMAP_DMIC_SYSCONFIG_REG 0x10 11*4882a593Smuzhiyun #define OMAP_DMIC_IRQSTATUS_RAW_REG 0x24 12*4882a593Smuzhiyun #define OMAP_DMIC_IRQSTATUS_REG 0x28 13*4882a593Smuzhiyun #define OMAP_DMIC_IRQENABLE_SET_REG 0x2C 14*4882a593Smuzhiyun #define OMAP_DMIC_IRQENABLE_CLR_REG 0x30 15*4882a593Smuzhiyun #define OMAP_DMIC_IRQWAKE_EN_REG 0x34 16*4882a593Smuzhiyun #define OMAP_DMIC_DMAENABLE_SET_REG 0x38 17*4882a593Smuzhiyun #define OMAP_DMIC_DMAENABLE_CLR_REG 0x3C 18*4882a593Smuzhiyun #define OMAP_DMIC_DMAWAKEEN_REG 0x40 19*4882a593Smuzhiyun #define OMAP_DMIC_CTRL_REG 0x44 20*4882a593Smuzhiyun #define OMAP_DMIC_DATA_REG 0x48 21*4882a593Smuzhiyun #define OMAP_DMIC_FIFO_CTRL_REG 0x4C 22*4882a593Smuzhiyun #define OMAP_DMIC_FIFO_DMIC1R_DATA_REG 0x50 23*4882a593Smuzhiyun #define OMAP_DMIC_FIFO_DMIC1L_DATA_REG 0x54 24*4882a593Smuzhiyun #define OMAP_DMIC_FIFO_DMIC2R_DATA_REG 0x58 25*4882a593Smuzhiyun #define OMAP_DMIC_FIFO_DMIC2L_DATA_REG 0x5C 26*4882a593Smuzhiyun #define OMAP_DMIC_FIFO_DMIC3R_DATA_REG 0x60 27*4882a593Smuzhiyun #define OMAP_DMIC_FIFO_DMIC3L_DATA_REG 0x64 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR bit fields */ 30*4882a593Smuzhiyun #define OMAP_DMIC_IRQ (1 << 0) 31*4882a593Smuzhiyun #define OMAP_DMIC_IRQ_FULL (1 << 1) 32*4882a593Smuzhiyun #define OMAP_DMIC_IRQ_ALMST_EMPTY (1 << 2) 33*4882a593Smuzhiyun #define OMAP_DMIC_IRQ_EMPTY (1 << 3) 34*4882a593Smuzhiyun #define OMAP_DMIC_IRQ_MASK 0x07 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* DMIC_DMAENABLE bit fields */ 37*4882a593Smuzhiyun #define OMAP_DMIC_DMA_ENABLE 0x1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* DMIC_CTRL bit fields */ 40*4882a593Smuzhiyun #define OMAP_DMIC_UP1_ENABLE (1 << 0) 41*4882a593Smuzhiyun #define OMAP_DMIC_UP2_ENABLE (1 << 1) 42*4882a593Smuzhiyun #define OMAP_DMIC_UP3_ENABLE (1 << 2) 43*4882a593Smuzhiyun #define OMAP_DMIC_UP_ENABLE_MASK 0x7 44*4882a593Smuzhiyun #define OMAP_DMIC_FORMAT (1 << 3) 45*4882a593Smuzhiyun #define OMAP_DMIC_POLAR1 (1 << 4) 46*4882a593Smuzhiyun #define OMAP_DMIC_POLAR2 (1 << 5) 47*4882a593Smuzhiyun #define OMAP_DMIC_POLAR3 (1 << 6) 48*4882a593Smuzhiyun #define OMAP_DMIC_POLAR_MASK (0x7 << 4) 49*4882a593Smuzhiyun #define OMAP_DMIC_CLK_DIV(x) (((x) & 0x7) << 7) 50*4882a593Smuzhiyun #define OMAP_DMIC_CLK_DIV_MASK (0x7 << 7) 51*4882a593Smuzhiyun #define OMAP_DMIC_RESET (1 << 10) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define OMAP_DMICOUTFORMAT_LJUST (0 << 3) 54*4882a593Smuzhiyun #define OMAP_DMICOUTFORMAT_RJUST (1 << 3) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* DMIC_FIFO_CTRL bit fields */ 57*4882a593Smuzhiyun #define OMAP_DMIC_THRES_MAX 0xF 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun enum omap_dmic_clk { 60*4882a593Smuzhiyun OMAP_DMIC_SYSCLK_PAD_CLKS, /* PAD_CLKS */ 61*4882a593Smuzhiyun OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS, /* SLIMBUS_CLK */ 62*4882a593Smuzhiyun OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS, /* DMIC_SYNC_MUX_CLK */ 63*4882a593Smuzhiyun OMAP_DMIC_ABE_DMIC_CLK, /* abe_dmic_clk */ 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif 67