1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tegra_cif.h - TEGRA Audio CIF Programming 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __TEGRA_CIF_H__ 10*4882a593Smuzhiyun #define __TEGRA_CIF_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/regmap.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define TEGRA_ACIF_CTRL_FIFO_TH_SHIFT 24 15*4882a593Smuzhiyun #define TEGRA_ACIF_CTRL_AUDIO_CH_SHIFT 20 16*4882a593Smuzhiyun #define TEGRA_ACIF_CTRL_CLIENT_CH_SHIFT 16 17*4882a593Smuzhiyun #define TEGRA_ACIF_CTRL_AUDIO_BITS_SHIFT 12 18*4882a593Smuzhiyun #define TEGRA_ACIF_CTRL_CLIENT_BITS_SHIFT 8 19*4882a593Smuzhiyun #define TEGRA_ACIF_CTRL_EXPAND_SHIFT 6 20*4882a593Smuzhiyun #define TEGRA_ACIF_CTRL_STEREO_CONV_SHIFT 4 21*4882a593Smuzhiyun #define TEGRA_ACIF_CTRL_REPLICATE_SHIFT 3 22*4882a593Smuzhiyun #define TEGRA_ACIF_CTRL_TRUNCATE_SHIFT 1 23*4882a593Smuzhiyun #define TEGRA_ACIF_CTRL_MONO_CONV_SHIFT 0 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* AUDIO/CLIENT_BITS values */ 26*4882a593Smuzhiyun #define TEGRA_ACIF_BITS_8 1 27*4882a593Smuzhiyun #define TEGRA_ACIF_BITS_16 3 28*4882a593Smuzhiyun #define TEGRA_ACIF_BITS_24 5 29*4882a593Smuzhiyun #define TEGRA_ACIF_BITS_32 7 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define TEGRA_ACIF_UPDATE_MASK 0x3ffffffb 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct tegra_cif_conf { 34*4882a593Smuzhiyun unsigned int threshold; 35*4882a593Smuzhiyun unsigned int audio_ch; 36*4882a593Smuzhiyun unsigned int client_ch; 37*4882a593Smuzhiyun unsigned int audio_bits; 38*4882a593Smuzhiyun unsigned int client_bits; 39*4882a593Smuzhiyun unsigned int expand; 40*4882a593Smuzhiyun unsigned int stereo_conv; 41*4882a593Smuzhiyun unsigned int replicate; 42*4882a593Smuzhiyun unsigned int truncate; 43*4882a593Smuzhiyun unsigned int mono_conv; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun tegra_set_cif(struct regmap * regmap,unsigned int reg,struct tegra_cif_conf * conf)46*4882a593Smuzhiyunstatic inline void tegra_set_cif(struct regmap *regmap, unsigned int reg, 47*4882a593Smuzhiyun struct tegra_cif_conf *conf) 48*4882a593Smuzhiyun { 49*4882a593Smuzhiyun unsigned int value; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun value = (conf->threshold << TEGRA_ACIF_CTRL_FIFO_TH_SHIFT) | 52*4882a593Smuzhiyun ((conf->audio_ch - 1) << TEGRA_ACIF_CTRL_AUDIO_CH_SHIFT) | 53*4882a593Smuzhiyun ((conf->client_ch - 1) << TEGRA_ACIF_CTRL_CLIENT_CH_SHIFT) | 54*4882a593Smuzhiyun (conf->audio_bits << TEGRA_ACIF_CTRL_AUDIO_BITS_SHIFT) | 55*4882a593Smuzhiyun (conf->client_bits << TEGRA_ACIF_CTRL_CLIENT_BITS_SHIFT) | 56*4882a593Smuzhiyun (conf->expand << TEGRA_ACIF_CTRL_EXPAND_SHIFT) | 57*4882a593Smuzhiyun (conf->stereo_conv << TEGRA_ACIF_CTRL_STEREO_CONV_SHIFT) | 58*4882a593Smuzhiyun (conf->replicate << TEGRA_ACIF_CTRL_REPLICATE_SHIFT) | 59*4882a593Smuzhiyun (conf->truncate << TEGRA_ACIF_CTRL_TRUNCATE_SHIFT) | 60*4882a593Smuzhiyun (conf->mono_conv << TEGRA_ACIF_CTRL_MONO_CONV_SHIFT); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun regmap_update_bits(regmap, reg, TEGRA_ACIF_UPDATE_MASK, value); 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif 66