1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tegra_asoc_utils.h - Definitions for Tegra DAS driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Stephen Warren <swarren@nvidia.com> 6*4882a593Smuzhiyun * Copyright (C) 2010,2012 - NVIDIA, Inc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __TEGRA_ASOC_UTILS_H__ 10*4882a593Smuzhiyun #define __TEGRA_ASOC_UTILS_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct clk; 13*4882a593Smuzhiyun struct device; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum tegra_asoc_utils_soc { 16*4882a593Smuzhiyun TEGRA_ASOC_UTILS_SOC_TEGRA20, 17*4882a593Smuzhiyun TEGRA_ASOC_UTILS_SOC_TEGRA30, 18*4882a593Smuzhiyun TEGRA_ASOC_UTILS_SOC_TEGRA114, 19*4882a593Smuzhiyun TEGRA_ASOC_UTILS_SOC_TEGRA124, 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct tegra_asoc_utils_data { 23*4882a593Smuzhiyun struct device *dev; 24*4882a593Smuzhiyun enum tegra_asoc_utils_soc soc; 25*4882a593Smuzhiyun struct clk *clk_pll_a; 26*4882a593Smuzhiyun struct clk *clk_pll_a_out0; 27*4882a593Smuzhiyun struct clk *clk_cdev1; 28*4882a593Smuzhiyun int set_baseclock; 29*4882a593Smuzhiyun int set_mclk; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate, 33*4882a593Smuzhiyun int mclk); 34*4882a593Smuzhiyun int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data); 35*4882a593Smuzhiyun int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data, 36*4882a593Smuzhiyun struct device *dev); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif 39