1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tegra210_dmic.h - Definitions for Tegra210 DMIC driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __TEGRA210_DMIC_H__ 10*4882a593Smuzhiyun #define __TEGRA210_DMIC_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Register offsets from DMIC BASE */ 13*4882a593Smuzhiyun #define TEGRA210_DMIC_TX_STATUS 0x0c 14*4882a593Smuzhiyun #define TEGRA210_DMIC_TX_INT_STATUS 0x10 15*4882a593Smuzhiyun #define TEGRA210_DMIC_TX_INT_MASK 0x14 16*4882a593Smuzhiyun #define TEGRA210_DMIC_TX_INT_SET 0x18 17*4882a593Smuzhiyun #define TEGRA210_DMIC_TX_INT_CLEAR 0x1c 18*4882a593Smuzhiyun #define TEGRA210_DMIC_TX_CIF_CTRL 0x20 19*4882a593Smuzhiyun #define TEGRA210_DMIC_ENABLE 0x40 20*4882a593Smuzhiyun #define TEGRA210_DMIC_SOFT_RESET 0x44 21*4882a593Smuzhiyun #define TEGRA210_DMIC_CG 0x48 22*4882a593Smuzhiyun #define TEGRA210_DMIC_STATUS 0x4c 23*4882a593Smuzhiyun #define TEGRA210_DMIC_INT_STATUS 0x50 24*4882a593Smuzhiyun #define TEGRA210_DMIC_CTRL 0x64 25*4882a593Smuzhiyun #define TEGRA210_DMIC_DBG_CTRL 0x70 26*4882a593Smuzhiyun #define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 0x88 27*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_FILTER_GAIN 0x8c 28*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_0 0x90 29*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_1 0x94 30*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_2 0x98 31*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_3 0x9c 32*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_4 0xa0 33*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_0 0xa4 34*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_1 0xa8 35*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_2 0xac 36*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_3 0xb0 37*4882a593Smuzhiyun #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_4 0xb4 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Fields in TEGRA210_DMIC_CTRL */ 40*4882a593Smuzhiyun #define CH_SEL_SHIFT 8 41*4882a593Smuzhiyun #define TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK (0x3 << CH_SEL_SHIFT) 42*4882a593Smuzhiyun #define LRSEL_POL_SHIFT 4 43*4882a593Smuzhiyun #define TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT) 44*4882a593Smuzhiyun #define OSR_SHIFT 0 45*4882a593Smuzhiyun #define TEGRA210_DMIC_CTRL_OSR_MASK (0x3 << OSR_SHIFT) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define DMIC_OSR_FACTOR 64 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define DEFAULT_GAIN_Q23 0x800000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Max boost gain factor used for mixer control */ 52*4882a593Smuzhiyun #define MAX_BOOST_GAIN 25599 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun enum tegra_dmic_ch_select { 55*4882a593Smuzhiyun DMIC_CH_SELECT_LEFT, 56*4882a593Smuzhiyun DMIC_CH_SELECT_RIGHT, 57*4882a593Smuzhiyun DMIC_CH_SELECT_STEREO, 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun enum tegra_dmic_osr { 61*4882a593Smuzhiyun DMIC_OSR_64, 62*4882a593Smuzhiyun DMIC_OSR_128, 63*4882a593Smuzhiyun DMIC_OSR_256, 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun enum tegra_dmic_lrsel { 67*4882a593Smuzhiyun DMIC_LRSEL_LEFT, 68*4882a593Smuzhiyun DMIC_LRSEL_RIGHT, 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct tegra210_dmic { 72*4882a593Smuzhiyun struct clk *clk_dmic; 73*4882a593Smuzhiyun struct regmap *regmap; 74*4882a593Smuzhiyun unsigned int mono_to_stereo; 75*4882a593Smuzhiyun unsigned int stereo_to_mono; 76*4882a593Smuzhiyun unsigned int boost_gain; 77*4882a593Smuzhiyun unsigned int ch_select; 78*4882a593Smuzhiyun unsigned int osr_val; 79*4882a593Smuzhiyun unsigned int lrsel; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif 83