xref: /OK3568_Linux_fs/kernel/sound/soc/tegra/tegra210_ahub.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * tegra210_ahub.h - TEGRA210 AHUB
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #ifndef __TEGRA210_AHUB__H__
10*4882a593Smuzhiyun #define __TEGRA210_AHUB__H__
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun /* Tegra210 specific */
13*4882a593Smuzhiyun #define TEGRA210_XBAR_PART1_RX				0x200
14*4882a593Smuzhiyun #define TEGRA210_XBAR_PART2_RX				0x400
15*4882a593Smuzhiyun #define TEGRA210_XBAR_RX_STRIDE				0x4
16*4882a593Smuzhiyun #define TEGRA210_XBAR_AUDIO_RX_COUNT			90
17*4882a593Smuzhiyun #define TEGRA210_XBAR_REG_MASK_0			0xf1f03ff
18*4882a593Smuzhiyun #define TEGRA210_XBAR_REG_MASK_1			0x3f30031f
19*4882a593Smuzhiyun #define TEGRA210_XBAR_REG_MASK_2			0xff1cf313
20*4882a593Smuzhiyun #define TEGRA210_XBAR_REG_MASK_3			0x0
21*4882a593Smuzhiyun #define TEGRA210_XBAR_UPDATE_MAX_REG			3
22*4882a593Smuzhiyun /* Tegra186 specific */
23*4882a593Smuzhiyun #define TEGRA186_XBAR_PART3_RX				0x600
24*4882a593Smuzhiyun #define TEGRA186_XBAR_AUDIO_RX_COUNT			115
25*4882a593Smuzhiyun #define TEGRA186_XBAR_REG_MASK_0			0xf3fffff
26*4882a593Smuzhiyun #define TEGRA186_XBAR_REG_MASK_1			0x3f310f1f
27*4882a593Smuzhiyun #define TEGRA186_XBAR_REG_MASK_2			0xff3cf311
28*4882a593Smuzhiyun #define TEGRA186_XBAR_REG_MASK_3			0x3f0f00ff
29*4882a593Smuzhiyun #define TEGRA186_XBAR_UPDATE_MAX_REG			4
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX +		\
34*4882a593Smuzhiyun 	(TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1)))
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX +		\
37*4882a593Smuzhiyun 	(TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id))
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32)
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues)		\
44*4882a593Smuzhiyun 	{								\
45*4882a593Smuzhiyun 		.reg = xreg,						\
46*4882a593Smuzhiyun 		.shift_l = shift,					\
47*4882a593Smuzhiyun 		.shift_r = shift,					\
48*4882a593Smuzhiyun 		.items = xmax,						\
49*4882a593Smuzhiyun 		.texts = xtexts,					\
50*4882a593Smuzhiyun 		.values = xvalues,					\
51*4882a593Smuzhiyun 		.mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0		\
52*4882a593Smuzhiyun 	}
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, xtexts, xvalues)	\
55*4882a593Smuzhiyun 	static struct soc_enum name =					\
56*4882a593Smuzhiyun 		SOC_VALUE_ENUM_WIDE(xreg, shift, ARRAY_SIZE(xtexts),	\
57*4882a593Smuzhiyun 				    xtexts, xvalues)
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define MUX_ENUM_CTRL_DECL(ename, id)					\
60*4882a593Smuzhiyun 	SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0,		\
61*4882a593Smuzhiyun 				 tegra210_ahub_mux_texts,		\
62*4882a593Smuzhiyun 				 tegra210_ahub_mux_values);		\
63*4882a593Smuzhiyun 	static const struct snd_kcontrol_new ename##_control =		\
64*4882a593Smuzhiyun 		SOC_DAPM_ENUM_EXT("Route", ename##_enum,		\
65*4882a593Smuzhiyun 				  tegra_ahub_get_value_enum,		\
66*4882a593Smuzhiyun 				  tegra_ahub_put_value_enum)
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #define MUX_ENUM_CTRL_DECL_186(ename, id)				\
69*4882a593Smuzhiyun 	SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0,		\
70*4882a593Smuzhiyun 				 tegra186_ahub_mux_texts,		\
71*4882a593Smuzhiyun 				 tegra186_ahub_mux_values);		\
72*4882a593Smuzhiyun 	static const struct snd_kcontrol_new ename##_control =		\
73*4882a593Smuzhiyun 		SOC_DAPM_ENUM_EXT("Route", ename##_enum,		\
74*4882a593Smuzhiyun 				  tegra_ahub_get_value_enum,		\
75*4882a593Smuzhiyun 				  tegra_ahub_put_value_enum)
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define WIDGETS(sname, ename)						     \
78*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0),  \
79*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
80*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX(sname " Mux", SND_SOC_NOPM, 0, 0,		     \
81*4882a593Smuzhiyun 			 &ename##_control)
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define TX_WIDGETS(sname)						    \
84*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
85*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0)
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun #define DAI(sname)							\
88*4882a593Smuzhiyun 	{								\
89*4882a593Smuzhiyun 		.name = "XBAR-" #sname,					\
90*4882a593Smuzhiyun 		.playback = {						\
91*4882a593Smuzhiyun 			.stream_name = #sname " XBAR-Playback",		\
92*4882a593Smuzhiyun 			.channels_min = 1,				\
93*4882a593Smuzhiyun 			.channels_max = 16,				\
94*4882a593Smuzhiyun 			.rates = SNDRV_PCM_RATE_8000_192000,		\
95*4882a593Smuzhiyun 			.formats = SNDRV_PCM_FMTBIT_S8 |		\
96*4882a593Smuzhiyun 				SNDRV_PCM_FMTBIT_S16_LE |		\
97*4882a593Smuzhiyun 				SNDRV_PCM_FMTBIT_S24_LE |		\
98*4882a593Smuzhiyun 				SNDRV_PCM_FMTBIT_S32_LE,		\
99*4882a593Smuzhiyun 		},							\
100*4882a593Smuzhiyun 		.capture = {						\
101*4882a593Smuzhiyun 			.stream_name = #sname " XBAR-Capture",		\
102*4882a593Smuzhiyun 			.channels_min = 1,				\
103*4882a593Smuzhiyun 			.channels_max = 16,				\
104*4882a593Smuzhiyun 			.rates = SNDRV_PCM_RATE_8000_192000,		\
105*4882a593Smuzhiyun 			.formats = SNDRV_PCM_FMTBIT_S8 |		\
106*4882a593Smuzhiyun 				SNDRV_PCM_FMTBIT_S16_LE |		\
107*4882a593Smuzhiyun 				SNDRV_PCM_FMTBIT_S24_LE |		\
108*4882a593Smuzhiyun 				SNDRV_PCM_FMTBIT_S32_LE,		\
109*4882a593Smuzhiyun 		},							\
110*4882a593Smuzhiyun 	}
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun struct tegra_ahub_soc_data {
113*4882a593Smuzhiyun 	const struct regmap_config *regmap_config;
114*4882a593Smuzhiyun 	const struct snd_soc_component_driver *cmpnt_drv;
115*4882a593Smuzhiyun 	struct snd_soc_dai_driver *dai_drv;
116*4882a593Smuzhiyun 	unsigned int mask[4];
117*4882a593Smuzhiyun 	unsigned int reg_count;
118*4882a593Smuzhiyun 	unsigned int num_dais;
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun struct tegra_ahub {
122*4882a593Smuzhiyun 	const struct tegra_ahub_soc_data *soc_data;
123*4882a593Smuzhiyun 	struct regmap *regmap;
124*4882a593Smuzhiyun 	struct clk *clk;
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #endif
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