1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tegra210_admaif.h - Tegra ADMAIF registers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __TEGRA_ADMAIF_H__ 10*4882a593Smuzhiyun #define __TEGRA_ADMAIF_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define TEGRA_ADMAIF_CHANNEL_REG_STRIDE 0x40 13*4882a593Smuzhiyun /* Tegra210 specific */ 14*4882a593Smuzhiyun #define TEGRA210_ADMAIF_LAST_REG 0x75f 15*4882a593Smuzhiyun #define TEGRA210_ADMAIF_CHANNEL_COUNT 10 16*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX_BASE 0x0 17*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX_BASE 0x300 18*4882a593Smuzhiyun #define TEGRA210_ADMAIF_GLOBAL_BASE 0x700 19*4882a593Smuzhiyun /* Tegra186 specific */ 20*4882a593Smuzhiyun #define TEGRA186_ADMAIF_LAST_REG 0xd5f 21*4882a593Smuzhiyun #define TEGRA186_ADMAIF_CHANNEL_COUNT 20 22*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX_BASE 0x0 23*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX_BASE 0x500 24*4882a593Smuzhiyun #define TEGRA186_ADMAIF_GLOBAL_BASE 0xd00 25*4882a593Smuzhiyun /* Global registers */ 26*4882a593Smuzhiyun #define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0 27*4882a593Smuzhiyun #define TEGRA_ADMAIF_GLOBAL_CG_0 0x8 28*4882a593Smuzhiyun #define TEGRA_ADMAIF_GLOBAL_STATUS 0x10 29*4882a593Smuzhiyun #define TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS 0x20 30*4882a593Smuzhiyun #define TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS 0x24 31*4882a593Smuzhiyun /* RX channel registers */ 32*4882a593Smuzhiyun #define TEGRA_ADMAIF_RX_ENABLE 0x0 33*4882a593Smuzhiyun #define TEGRA_ADMAIF_RX_SOFT_RESET 0x4 34*4882a593Smuzhiyun #define TEGRA_ADMAIF_RX_STATUS 0xc 35*4882a593Smuzhiyun #define TEGRA_ADMAIF_RX_INT_STATUS 0x10 36*4882a593Smuzhiyun #define TEGRA_ADMAIF_RX_INT_MASK 0x14 37*4882a593Smuzhiyun #define TEGRA_ADMAIF_RX_INT_SET 0x18 38*4882a593Smuzhiyun #define TEGRA_ADMAIF_RX_INT_CLEAR 0x1c 39*4882a593Smuzhiyun #define TEGRA_ADMAIF_CH_ACIF_RX_CTRL 0x20 40*4882a593Smuzhiyun #define TEGRA_ADMAIF_RX_FIFO_CTRL 0x28 41*4882a593Smuzhiyun #define TEGRA_ADMAIF_RX_FIFO_READ 0x2c 42*4882a593Smuzhiyun /* TX channel registers */ 43*4882a593Smuzhiyun #define TEGRA_ADMAIF_TX_ENABLE 0x0 44*4882a593Smuzhiyun #define TEGRA_ADMAIF_TX_SOFT_RESET 0x4 45*4882a593Smuzhiyun #define TEGRA_ADMAIF_TX_STATUS 0xc 46*4882a593Smuzhiyun #define TEGRA_ADMAIF_TX_INT_STATUS 0x10 47*4882a593Smuzhiyun #define TEGRA_ADMAIF_TX_INT_MASK 0x14 48*4882a593Smuzhiyun #define TEGRA_ADMAIF_TX_INT_SET 0x18 49*4882a593Smuzhiyun #define TEGRA_ADMAIF_TX_INT_CLEAR 0x1c 50*4882a593Smuzhiyun #define TEGRA_ADMAIF_CH_ACIF_TX_CTRL 0x20 51*4882a593Smuzhiyun #define TEGRA_ADMAIF_TX_FIFO_CTRL 0x28 52*4882a593Smuzhiyun #define TEGRA_ADMAIF_TX_FIFO_WRITE 0x2c 53*4882a593Smuzhiyun /* Bit fields */ 54*4882a593Smuzhiyun #define PACK8_EN_SHIFT 31 55*4882a593Smuzhiyun #define PACK8_EN_MASK BIT(PACK8_EN_SHIFT) 56*4882a593Smuzhiyun #define PACK8_EN BIT(PACK8_EN_SHIFT) 57*4882a593Smuzhiyun #define PACK16_EN_SHIFT 30 58*4882a593Smuzhiyun #define PACK16_EN_MASK BIT(PACK16_EN_SHIFT) 59*4882a593Smuzhiyun #define PACK16_EN BIT(PACK16_EN_SHIFT) 60*4882a593Smuzhiyun #define TX_ENABLE_SHIFT 0 61*4882a593Smuzhiyun #define TX_ENABLE_MASK BIT(TX_ENABLE_SHIFT) 62*4882a593Smuzhiyun #define TX_ENABLE BIT(TX_ENABLE_SHIFT) 63*4882a593Smuzhiyun #define RX_ENABLE_SHIFT 0 64*4882a593Smuzhiyun #define RX_ENABLE_MASK BIT(RX_ENABLE_SHIFT) 65*4882a593Smuzhiyun #define RX_ENABLE BIT(RX_ENABLE_SHIFT) 66*4882a593Smuzhiyun #define SW_RESET_MASK 1 67*4882a593Smuzhiyun #define SW_RESET 1 68*4882a593Smuzhiyun /* Default values - Tegra210 */ 69*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300 70*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304 71*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000208 72*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000020b 73*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020e 74*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000211 75*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000214 76*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000217 77*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021a 78*4882a593Smuzhiyun #define TEGRA210_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021d 79*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300 80*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304 81*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800208 82*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0180020b 83*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020e 84*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800211 85*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800214 86*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800217 87*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021a 88*4882a593Smuzhiyun #define TEGRA210_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021d 89*4882a593Smuzhiyun /* Default values - Tegra186 */ 90*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300 91*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304 92*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000308 93*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000030c 94*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x00000210 95*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000213 96*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000216 97*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000219 98*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021c 99*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021f 100*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x00000222 101*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000225 102*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000228 103*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x0000022b 104*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022e 105*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x00000231 106*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000234 107*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000237 108*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x0000023a 109*4882a593Smuzhiyun #define TEGRA186_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x0000023d 110*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300 111*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304 112*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x02000308 113*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0200030c 114*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x01800210 115*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800213 116*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800216 117*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800219 118*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021c 119*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021f 120*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x01800222 121*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800225 122*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800228 123*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x0180022b 124*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022e 125*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x01800231 126*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800234 127*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800237 128*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x0180023a 129*4882a593Smuzhiyun #define TEGRA186_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x0180023d 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun enum { 132*4882a593Smuzhiyun DATA_8BIT, 133*4882a593Smuzhiyun DATA_16BIT, 134*4882a593Smuzhiyun DATA_32BIT 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun enum { 138*4882a593Smuzhiyun ADMAIF_RX_PATH, 139*4882a593Smuzhiyun ADMAIF_TX_PATH, 140*4882a593Smuzhiyun ADMAIF_PATHS, 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun struct tegra_admaif_soc_data { 144*4882a593Smuzhiyun const struct snd_soc_component_driver *cmpnt; 145*4882a593Smuzhiyun const struct regmap_config *regmap_conf; 146*4882a593Smuzhiyun struct snd_soc_dai_driver *dais; 147*4882a593Smuzhiyun unsigned int global_base; 148*4882a593Smuzhiyun unsigned int tx_base; 149*4882a593Smuzhiyun unsigned int rx_base; 150*4882a593Smuzhiyun unsigned int num_ch; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun struct tegra_admaif { 154*4882a593Smuzhiyun struct snd_dmaengine_dai_dma_data *capture_dma_data; 155*4882a593Smuzhiyun struct snd_dmaengine_dai_dma_data *playback_dma_data; 156*4882a593Smuzhiyun const struct tegra_admaif_soc_data *soc_data; 157*4882a593Smuzhiyun unsigned int *mono_to_stereo[ADMAIF_PATHS]; 158*4882a593Smuzhiyun unsigned int *stereo_to_mono[ADMAIF_PATHS]; 159*4882a593Smuzhiyun struct regmap *regmap; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #endif 163