1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tegra20_das.h - Definitions for Tegra20 DAS driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Stephen Warren <swarren@nvidia.com> 6*4882a593Smuzhiyun * Copyright (C) 2010,2012 - NVIDIA, Inc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __TEGRA20_DAS_H__ 10*4882a593Smuzhiyun #define __TEGRA20_DAS_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Register TEGRA20_DAS_DAP_CTRL_SEL */ 13*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL 0x00 14*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5 15*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4 16*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31 17*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1 18*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30 19*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1 20*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29 21*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1 22*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0 23*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */ 26*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_SEL_DAC1 0 27*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_SEL_DAC2 1 28*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_SEL_DAC3 2 29*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_SEL_DAP1 16 30*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_SEL_DAP2 17 31*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_SEL_DAP3 18 32*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_SEL_DAP4 19 33*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_SEL_DAP5 20 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */ 36*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40 37*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3 38*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4 39*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28 40*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4 41*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24 42*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4 43*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0 44*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * Values for: 48*4882a593Smuzhiyun * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL 49*4882a593Smuzhiyun * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL 50*4882a593Smuzhiyun * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_SEL_DAP1 0 53*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_SEL_DAP2 1 54*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_SEL_DAP3 2 55*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_SEL_DAP4 3 56*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_SEL_DAP5 4 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * Names/IDs of the DACs/DAPs. 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_ID_1 0 63*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_ID_2 1 64*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_ID_3 2 65*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_ID_4 3 66*4882a593Smuzhiyun #define TEGRA20_DAS_DAP_ID_5 4 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_ID_1 0 69*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_ID_2 1 70*4882a593Smuzhiyun #define TEGRA20_DAS_DAC_ID_3 2 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun struct tegra20_das { 73*4882a593Smuzhiyun struct device *dev; 74*4882a593Smuzhiyun struct regmap *regmap; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * Terminology: 79*4882a593Smuzhiyun * DAS: Digital audio switch (HW module controlled by this driver) 80*4882a593Smuzhiyun * DAP: Digital audio port (port/pins on Tegra device) 81*4882a593Smuzhiyun * DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere) 82*4882a593Smuzhiyun * 83*4882a593Smuzhiyun * The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific 84*4882a593Smuzhiyun * DAC, or another DAP. When DAPs are connected, one must be the master and 85*4882a593Smuzhiyun * one the slave. Each DAC allows selection of a specific DAP for input, to 86*4882a593Smuzhiyun * cater for the case where N DAPs are connected to 1 DAC for broadcast 87*4882a593Smuzhiyun * output. 88*4882a593Smuzhiyun * 89*4882a593Smuzhiyun * This driver is dumb; no attempt is made to ensure that a valid routing 90*4882a593Smuzhiyun * configuration is programmed. 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* 94*4882a593Smuzhiyun * Connect a DAP to a DAC 95*4882a593Smuzhiyun * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_* 96*4882a593Smuzhiyun * dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC* 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun extern int tegra20_das_connect_dap_to_dac(int dap_id, int dac_sel); 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * Connect a DAP to another DAP 102*4882a593Smuzhiyun * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_* 103*4882a593Smuzhiyun * other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP* 104*4882a593Smuzhiyun * master: Is this DAP the master (1) or slave (0) 105*4882a593Smuzhiyun * sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0) 106*4882a593Smuzhiyun * sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0) 107*4882a593Smuzhiyun */ 108*4882a593Smuzhiyun extern int tegra20_das_connect_dap_to_dap(int dap_id, int other_dap_sel, 109*4882a593Smuzhiyun int master, int sdata1rx, 110*4882a593Smuzhiyun int sdata2rx); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * Connect a DAC's input to a DAP 114*4882a593Smuzhiyun * (DAC outputs are selected by the DAP) 115*4882a593Smuzhiyun * dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_* 116*4882a593Smuzhiyun * dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP* 117*4882a593Smuzhiyun */ 118*4882a593Smuzhiyun extern int tegra20_das_connect_dac_to_dap(int dac_id, int dap_sel); 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif 121