xref: /OK3568_Linux_fs/kernel/sound/soc/tegra/tegra20_das.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * tegra20_das.c - Tegra20 DAS driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Stephen Warren <swarren@nvidia.com>
6*4882a593Smuzhiyun  * Copyright (C) 2010 - NVIDIA, Inc.
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <sound/soc.h>
16*4882a593Smuzhiyun #include "tegra20_das.h"
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define DRV_NAME "tegra20-das"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun static struct tegra20_das *das;
21*4882a593Smuzhiyun 
tegra20_das_write(u32 reg,u32 val)22*4882a593Smuzhiyun static inline void tegra20_das_write(u32 reg, u32 val)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun 	regmap_write(das->regmap, reg, val);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun 
tegra20_das_read(u32 reg)27*4882a593Smuzhiyun static inline u32 tegra20_das_read(u32 reg)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun 	u32 val;
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	regmap_read(das->regmap, reg, &val);
32*4882a593Smuzhiyun 	return val;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun 
tegra20_das_connect_dap_to_dac(int dap,int dac)35*4882a593Smuzhiyun int tegra20_das_connect_dap_to_dac(int dap, int dac)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun 	u32 addr;
38*4882a593Smuzhiyun 	u32 reg;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	if (!das)
41*4882a593Smuzhiyun 		return -ENODEV;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	addr = TEGRA20_DAS_DAP_CTRL_SEL +
44*4882a593Smuzhiyun 		(dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
45*4882a593Smuzhiyun 	reg = dac << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	tegra20_das_write(addr, reg);
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(tegra20_das_connect_dap_to_dac);
52*4882a593Smuzhiyun 
tegra20_das_connect_dap_to_dap(int dap,int otherdap,int master,int sdata1rx,int sdata2rx)53*4882a593Smuzhiyun int tegra20_das_connect_dap_to_dap(int dap, int otherdap, int master,
54*4882a593Smuzhiyun 				   int sdata1rx, int sdata2rx)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun 	u32 addr;
57*4882a593Smuzhiyun 	u32 reg;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	if (!das)
60*4882a593Smuzhiyun 		return -ENODEV;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	addr = TEGRA20_DAS_DAP_CTRL_SEL +
63*4882a593Smuzhiyun 		(dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
64*4882a593Smuzhiyun 	reg = otherdap << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P |
65*4882a593Smuzhiyun 		!!sdata2rx << TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P |
66*4882a593Smuzhiyun 		!!sdata1rx << TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P |
67*4882a593Smuzhiyun 		!!master << TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	tegra20_das_write(addr, reg);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(tegra20_das_connect_dap_to_dap);
74*4882a593Smuzhiyun 
tegra20_das_connect_dac_to_dap(int dac,int dap)75*4882a593Smuzhiyun int tegra20_das_connect_dac_to_dap(int dac, int dap)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun 	u32 addr;
78*4882a593Smuzhiyun 	u32 reg;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	if (!das)
81*4882a593Smuzhiyun 		return -ENODEV;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL +
84*4882a593Smuzhiyun 		(dac * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
85*4882a593Smuzhiyun 	reg = dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P |
86*4882a593Smuzhiyun 		dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P |
87*4882a593Smuzhiyun 		dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	tegra20_das_write(addr, reg);
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(tegra20_das_connect_dac_to_dap);
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define LAST_REG(name) \
96*4882a593Smuzhiyun 	(TEGRA20_DAS_##name + \
97*4882a593Smuzhiyun 	 (TEGRA20_DAS_##name##_STRIDE * (TEGRA20_DAS_##name##_COUNT - 1)))
98*4882a593Smuzhiyun 
tegra20_das_wr_rd_reg(struct device * dev,unsigned int reg)99*4882a593Smuzhiyun static bool tegra20_das_wr_rd_reg(struct device *dev, unsigned int reg)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	if (reg <= LAST_REG(DAP_CTRL_SEL))
102*4882a593Smuzhiyun 		return true;
103*4882a593Smuzhiyun 	if ((reg >= TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL) &&
104*4882a593Smuzhiyun 	    (reg <= LAST_REG(DAC_INPUT_DATA_CLK_SEL)))
105*4882a593Smuzhiyun 		return true;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	return false;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun static const struct regmap_config tegra20_das_regmap_config = {
111*4882a593Smuzhiyun 	.reg_bits = 32,
112*4882a593Smuzhiyun 	.reg_stride = 4,
113*4882a593Smuzhiyun 	.val_bits = 32,
114*4882a593Smuzhiyun 	.max_register = LAST_REG(DAC_INPUT_DATA_CLK_SEL),
115*4882a593Smuzhiyun 	.writeable_reg = tegra20_das_wr_rd_reg,
116*4882a593Smuzhiyun 	.readable_reg = tegra20_das_wr_rd_reg,
117*4882a593Smuzhiyun 	.cache_type = REGCACHE_FLAT,
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
tegra20_das_probe(struct platform_device * pdev)120*4882a593Smuzhiyun static int tegra20_das_probe(struct platform_device *pdev)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	void __iomem *regs;
123*4882a593Smuzhiyun 	int ret = 0;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	if (das)
126*4882a593Smuzhiyun 		return -ENODEV;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	das = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_das), GFP_KERNEL);
129*4882a593Smuzhiyun 	if (!das) {
130*4882a593Smuzhiyun 		ret = -ENOMEM;
131*4882a593Smuzhiyun 		goto err;
132*4882a593Smuzhiyun 	}
133*4882a593Smuzhiyun 	das->dev = &pdev->dev;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	regs = devm_platform_ioremap_resource(pdev, 0);
136*4882a593Smuzhiyun 	if (IS_ERR(regs)) {
137*4882a593Smuzhiyun 		ret = PTR_ERR(regs);
138*4882a593Smuzhiyun 		goto err;
139*4882a593Smuzhiyun 	}
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	das->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
142*4882a593Smuzhiyun 					    &tegra20_das_regmap_config);
143*4882a593Smuzhiyun 	if (IS_ERR(das->regmap)) {
144*4882a593Smuzhiyun 		dev_err(&pdev->dev, "regmap init failed\n");
145*4882a593Smuzhiyun 		ret = PTR_ERR(das->regmap);
146*4882a593Smuzhiyun 		goto err;
147*4882a593Smuzhiyun 	}
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	ret = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_1,
150*4882a593Smuzhiyun 					     TEGRA20_DAS_DAP_SEL_DAC1);
151*4882a593Smuzhiyun 	if (ret) {
152*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Can't set up DAS DAP connection\n");
153*4882a593Smuzhiyun 		goto err;
154*4882a593Smuzhiyun 	}
155*4882a593Smuzhiyun 	ret = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAC_ID_1,
156*4882a593Smuzhiyun 					     TEGRA20_DAS_DAC_SEL_DAP1);
157*4882a593Smuzhiyun 	if (ret) {
158*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Can't set up DAS DAC connection\n");
159*4882a593Smuzhiyun 		goto err;
160*4882a593Smuzhiyun 	}
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	ret = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_3,
163*4882a593Smuzhiyun 					     TEGRA20_DAS_DAP_SEL_DAC3);
164*4882a593Smuzhiyun 	if (ret) {
165*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Can't set up DAS DAP connection\n");
166*4882a593Smuzhiyun 		goto err;
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun 	ret = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAC_ID_3,
169*4882a593Smuzhiyun 					     TEGRA20_DAS_DAC_SEL_DAP3);
170*4882a593Smuzhiyun 	if (ret) {
171*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Can't set up DAS DAC connection\n");
172*4882a593Smuzhiyun 		goto err;
173*4882a593Smuzhiyun 	}
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	platform_set_drvdata(pdev, das);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	return 0;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun err:
180*4882a593Smuzhiyun 	das = NULL;
181*4882a593Smuzhiyun 	return ret;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun 
tegra20_das_remove(struct platform_device * pdev)184*4882a593Smuzhiyun static int tegra20_das_remove(struct platform_device *pdev)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun 	if (!das)
187*4882a593Smuzhiyun 		return -ENODEV;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	das = NULL;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	return 0;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun static const struct of_device_id tegra20_das_of_match[] = {
195*4882a593Smuzhiyun 	{ .compatible = "nvidia,tegra20-das", },
196*4882a593Smuzhiyun 	{},
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun static struct platform_driver tegra20_das_driver = {
200*4882a593Smuzhiyun 	.probe = tegra20_das_probe,
201*4882a593Smuzhiyun 	.remove = tegra20_das_remove,
202*4882a593Smuzhiyun 	.driver = {
203*4882a593Smuzhiyun 		.name = DRV_NAME,
204*4882a593Smuzhiyun 		.of_match_table = tegra20_das_of_match,
205*4882a593Smuzhiyun 	},
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun module_platform_driver(tegra20_das_driver);
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
210*4882a593Smuzhiyun MODULE_DESCRIPTION("Tegra20 DAS driver");
211*4882a593Smuzhiyun MODULE_LICENSE("GPL");
212*4882a593Smuzhiyun MODULE_ALIAS("platform:" DRV_NAME);
213*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tegra20_das_of_match);
214