1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tegra20_ac97.h - Definitions for the Tegra20 AC97 controller driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Partly based on code copyright/by: 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Copyright (c) 2011,2012 Toradex Inc. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __TEGRA20_AC97_H__ 13*4882a593Smuzhiyun #define __TEGRA20_AC97_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include "tegra_pcm.h" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL 0x00 18*4882a593Smuzhiyun #define TEGRA20_AC97_CMD 0x04 19*4882a593Smuzhiyun #define TEGRA20_AC97_STATUS1 0x08 20*4882a593Smuzhiyun /* ... */ 21*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO1_SCR 0x1c 22*4882a593Smuzhiyun /* ... */ 23*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_TX1 0x40 24*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_RX1 0x80 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* TEGRA20_AC97_CTRL */ 27*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_STM2_EN (1 << 16) 28*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_DOUBLE_SAMPLING_EN (1 << 11) 29*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_IO_CNTRL_EN (1 << 10) 30*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_HSET_DAC_EN (1 << 9) 31*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_LINE2_DAC_EN (1 << 8) 32*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_PCM_LFE_EN (1 << 7) 33*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_PCM_SUR_EN (1 << 6) 34*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_PCM_CEN_DAC_EN (1 << 5) 35*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_LINE1_DAC_EN (1 << 4) 36*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_PCM_DAC_EN (1 << 3) 37*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_COLD_RESET (1 << 2) 38*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_WARM_RESET (1 << 1) 39*4882a593Smuzhiyun #define TEGRA20_AC97_CTRL_STM_EN (1 << 0) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* TEGRA20_AC97_CMD */ 42*4882a593Smuzhiyun #define TEGRA20_AC97_CMD_CMD_ADDR_SHIFT 24 43*4882a593Smuzhiyun #define TEGRA20_AC97_CMD_CMD_ADDR_MASK (0xff << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) 44*4882a593Smuzhiyun #define TEGRA20_AC97_CMD_CMD_DATA_SHIFT 8 45*4882a593Smuzhiyun #define TEGRA20_AC97_CMD_CMD_DATA_MASK (0xffff << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) 46*4882a593Smuzhiyun #define TEGRA20_AC97_CMD_CMD_ID_SHIFT 2 47*4882a593Smuzhiyun #define TEGRA20_AC97_CMD_CMD_ID_MASK (0x3 << TEGRA20_AC97_CMD_CMD_ID_SHIFT) 48*4882a593Smuzhiyun #define TEGRA20_AC97_CMD_BUSY (1 << 0) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* TEGRA20_AC97_STATUS1 */ 51*4882a593Smuzhiyun #define TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT 24 52*4882a593Smuzhiyun #define TEGRA20_AC97_STATUS1_STA_ADDR1_MASK (0xff << TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT) 53*4882a593Smuzhiyun #define TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT 8 54*4882a593Smuzhiyun #define TEGRA20_AC97_STATUS1_STA_DATA1_MASK (0xffff << TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT) 55*4882a593Smuzhiyun #define TEGRA20_AC97_STATUS1_STA_VALID1 (1 << 2) 56*4882a593Smuzhiyun #define TEGRA20_AC97_STATUS1_STANDBY1 (1 << 1) 57*4882a593Smuzhiyun #define TEGRA20_AC97_STATUS1_CODEC1_RDY (1 << 0) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* TEGRA20_AC97_FIFO1_SCR */ 60*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT 27 61*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT) 62*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT 22 63*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT) 64*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_REC_OVERRUN_INT_STA (1 << 19) 65*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_PB_UNDERRUN_INT_STA (1 << 18) 66*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_REC_FORCE_MT (1 << 17) 67*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_PB_FORCE_MT (1 << 16) 68*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_REC_FULL_EN (1 << 15) 69*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_REC_3QRT_FULL_EN (1 << 14) 70*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_REC_QRT_FULL_EN (1 << 13) 71*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_REC_EMPTY_EN (1 << 12) 72*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_PB_NOT_FULL_EN (1 << 11) 73*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN (1 << 10) 74*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_PB_3QRT_MT_EN (1 << 9) 75*4882a593Smuzhiyun #define TEGRA20_AC97_FIFO_SCR_PB_EMPTY_MT_EN (1 << 8) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun struct tegra20_ac97 { 78*4882a593Smuzhiyun struct clk *clk_ac97; 79*4882a593Smuzhiyun struct snd_dmaengine_dai_dma_data capture_dma_data; 80*4882a593Smuzhiyun struct snd_dmaengine_dai_dma_data playback_dma_data; 81*4882a593Smuzhiyun struct regmap *regmap; 82*4882a593Smuzhiyun int reset_gpio; 83*4882a593Smuzhiyun int sync_gpio; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun #endif /* __TEGRA20_AC97_H__ */ 86