1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tegra186_dspk.h - Definitions for Tegra186 DSPK driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __TEGRA186_DSPK_H__ 10*4882a593Smuzhiyun #define __TEGRA186_DSPK_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Register offsets from DSPK BASE */ 13*4882a593Smuzhiyun #define TEGRA186_DSPK_RX_STATUS 0x0c 14*4882a593Smuzhiyun #define TEGRA186_DSPK_RX_INT_STATUS 0x10 15*4882a593Smuzhiyun #define TEGRA186_DSPK_RX_INT_MASK 0x14 16*4882a593Smuzhiyun #define TEGRA186_DSPK_RX_INT_SET 0x18 17*4882a593Smuzhiyun #define TEGRA186_DSPK_RX_INT_CLEAR 0x1c 18*4882a593Smuzhiyun #define TEGRA186_DSPK_RX_CIF_CTRL 0x20 19*4882a593Smuzhiyun #define TEGRA186_DSPK_ENABLE 0x40 20*4882a593Smuzhiyun #define TEGRA186_DSPK_SOFT_RESET 0x44 21*4882a593Smuzhiyun #define TEGRA186_DSPK_CG 0x48 22*4882a593Smuzhiyun #define TEGRA186_DSPK_STATUS 0x4c 23*4882a593Smuzhiyun #define TEGRA186_DSPK_INT_STATUS 0x50 24*4882a593Smuzhiyun #define TEGRA186_DSPK_CORE_CTRL 0x60 25*4882a593Smuzhiyun #define TEGRA186_DSPK_CODEC_CTRL 0x64 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* DSPK CORE CONTROL fields */ 28*4882a593Smuzhiyun #define CH_SEL_SHIFT 8 29*4882a593Smuzhiyun #define TEGRA186_DSPK_CHANNEL_SELECT_MASK (0x3 << CH_SEL_SHIFT) 30*4882a593Smuzhiyun #define DSPK_OSR_SHIFT 4 31*4882a593Smuzhiyun #define TEGRA186_DSPK_OSR_MASK (0x3 << DSPK_OSR_SHIFT) 32*4882a593Smuzhiyun #define LRSEL_POL_SHIFT 0 33*4882a593Smuzhiyun #define TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT) 34*4882a593Smuzhiyun #define TEGRA186_DSPK_RX_FIFO_DEPTH 64 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define DSPK_OSR_FACTOR 32 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* DSPK interface clock ratio */ 39*4882a593Smuzhiyun #define DSPK_CLK_RATIO 4 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun enum tegra_dspk_osr { 42*4882a593Smuzhiyun DSPK_OSR_32, 43*4882a593Smuzhiyun DSPK_OSR_64, 44*4882a593Smuzhiyun DSPK_OSR_128, 45*4882a593Smuzhiyun DSPK_OSR_256, 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun enum tegra_dspk_ch_sel { 49*4882a593Smuzhiyun DSPK_CH_SELECT_LEFT, 50*4882a593Smuzhiyun DSPK_CH_SELECT_RIGHT, 51*4882a593Smuzhiyun DSPK_CH_SELECT_STEREO, 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun enum tegra_dspk_lrsel { 55*4882a593Smuzhiyun DSPK_LRSEL_LEFT, 56*4882a593Smuzhiyun DSPK_LRSEL_RIGHT, 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct tegra186_dspk { 60*4882a593Smuzhiyun unsigned int rx_fifo_th; 61*4882a593Smuzhiyun unsigned int osr_val; 62*4882a593Smuzhiyun unsigned int lrsel; 63*4882a593Smuzhiyun unsigned int ch_sel; 64*4882a593Smuzhiyun unsigned int mono_to_stereo; 65*4882a593Smuzhiyun unsigned int stereo_to_mono; 66*4882a593Smuzhiyun struct clk *clk_dspk; 67*4882a593Smuzhiyun struct regmap *regmap; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif 71