1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (C) 2019 Spreadtrum Communications Inc.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/dma-mapping.h>
5*4882a593Smuzhiyun #include <linux/dmaengine.h>
6*4882a593Smuzhiyun #include <linux/dma/sprd-dma.h>
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <sound/pcm.h>
10*4882a593Smuzhiyun #include <sound/pcm_params.h>
11*4882a593Smuzhiyun #include <sound/soc.h>
12*4882a593Smuzhiyun #include <sound/compress_driver.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "sprd-pcm-dma.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define SPRD_COMPR_DMA_CHANS 2
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* Default values if userspace does not set */
19*4882a593Smuzhiyun #define SPRD_COMPR_MIN_FRAGMENT_SIZE SZ_8K
20*4882a593Smuzhiyun #define SPRD_COMPR_MAX_FRAGMENT_SIZE SZ_128K
21*4882a593Smuzhiyun #define SPRD_COMPR_MIN_NUM_FRAGMENTS 4
22*4882a593Smuzhiyun #define SPRD_COMPR_MAX_NUM_FRAGMENTS 64
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* DSP FIFO size */
25*4882a593Smuzhiyun #define SPRD_COMPR_MCDT_EMPTY_WMK 0
26*4882a593Smuzhiyun #define SPRD_COMPR_MCDT_FIFO_SIZE 512
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Stage 0 IRAM buffer size definition */
29*4882a593Smuzhiyun #define SPRD_COMPR_IRAM_BUF_SIZE SZ_32K
30*4882a593Smuzhiyun #define SPRD_COMPR_IRAM_INFO_SIZE (sizeof(struct sprd_compr_playinfo))
31*4882a593Smuzhiyun #define SPRD_COMPR_IRAM_LINKLIST_SIZE (1024 - SPRD_COMPR_IRAM_INFO_SIZE)
32*4882a593Smuzhiyun #define SPRD_COMPR_IRAM_SIZE (SPRD_COMPR_IRAM_BUF_SIZE + \
33*4882a593Smuzhiyun SPRD_COMPR_IRAM_INFO_SIZE + \
34*4882a593Smuzhiyun SPRD_COMPR_IRAM_LINKLIST_SIZE)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Stage 1 DDR buffer size definition */
37*4882a593Smuzhiyun #define SPRD_COMPR_AREA_BUF_SIZE SZ_2M
38*4882a593Smuzhiyun #define SPRD_COMPR_AREA_LINKLIST_SIZE 1024
39*4882a593Smuzhiyun #define SPRD_COMPR_AREA_SIZE (SPRD_COMPR_AREA_BUF_SIZE + \
40*4882a593Smuzhiyun SPRD_COMPR_AREA_LINKLIST_SIZE)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct sprd_compr_dma {
43*4882a593Smuzhiyun struct dma_chan *chan;
44*4882a593Smuzhiyun struct dma_async_tx_descriptor *desc;
45*4882a593Smuzhiyun dma_cookie_t cookie;
46*4882a593Smuzhiyun dma_addr_t phys;
47*4882a593Smuzhiyun void *virt;
48*4882a593Smuzhiyun int trans_len;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * The Spreadtrum Audio compress offload mode will use 2-stage DMA transfer to
53*4882a593Smuzhiyun * save power. That means we can request 2 dma channels, one for source channel,
54*4882a593Smuzhiyun * and another one for destination channel. Once the source channel's transaction
55*4882a593Smuzhiyun * is done, it will trigger the destination channel's transaction automatically
56*4882a593Smuzhiyun * by hardware signal.
57*4882a593Smuzhiyun *
58*4882a593Smuzhiyun * For 2-stage DMA transfer, we can allocate 2 buffers: IRAM buffer (always
59*4882a593Smuzhiyun * power-on) and DDR buffer. The source channel will transfer data from IRAM
60*4882a593Smuzhiyun * buffer to the DSP fifo to decoding/encoding, once IRAM buffer is empty by
61*4882a593Smuzhiyun * transferring done, the destination channel will start to transfer data from
62*4882a593Smuzhiyun * DDR buffer to IRAM buffer.
63*4882a593Smuzhiyun *
64*4882a593Smuzhiyun * Since the DSP fifo is only 512B, IRAM buffer is allocated by 32K, and DDR
65*4882a593Smuzhiyun * buffer is larger to 2M. That means only the IRAM 32k data is transferred
66*4882a593Smuzhiyun * done, we can wake up the AP system to transfer data from DDR to IRAM, and
67*4882a593Smuzhiyun * other time the AP system can be suspended to save power.
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun struct sprd_compr_stream {
70*4882a593Smuzhiyun struct snd_compr_stream *cstream;
71*4882a593Smuzhiyun struct sprd_compr_ops *compr_ops;
72*4882a593Smuzhiyun struct sprd_compr_dma dma[SPRD_COMPR_DMA_CHANS];
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* DMA engine channel number */
75*4882a593Smuzhiyun int num_channels;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Stage 0 IRAM buffer */
78*4882a593Smuzhiyun struct snd_dma_buffer iram_buffer;
79*4882a593Smuzhiyun /* Stage 1 DDR buffer */
80*4882a593Smuzhiyun struct snd_dma_buffer compr_buffer;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* DSP play information IRAM buffer */
83*4882a593Smuzhiyun dma_addr_t info_phys;
84*4882a593Smuzhiyun void *info_area;
85*4882a593Smuzhiyun int info_size;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Data size copied to IRAM buffer */
88*4882a593Smuzhiyun int copied_total;
89*4882a593Smuzhiyun /* Total received data size from userspace */
90*4882a593Smuzhiyun int received_total;
91*4882a593Smuzhiyun /* Stage 0 IRAM buffer received data size */
92*4882a593Smuzhiyun int received_stage0;
93*4882a593Smuzhiyun /* Stage 1 DDR buffer received data size */
94*4882a593Smuzhiyun int received_stage1;
95*4882a593Smuzhiyun /* Stage 1 DDR buffer pointer */
96*4882a593Smuzhiyun int stage1_pointer;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static int sprd_platform_compr_trigger(struct snd_soc_component *component,
100*4882a593Smuzhiyun struct snd_compr_stream *cstream,
101*4882a593Smuzhiyun int cmd);
102*4882a593Smuzhiyun
sprd_platform_compr_drain_notify(void * arg)103*4882a593Smuzhiyun static void sprd_platform_compr_drain_notify(void *arg)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun struct snd_compr_stream *cstream = arg;
106*4882a593Smuzhiyun struct snd_compr_runtime *runtime = cstream->runtime;
107*4882a593Smuzhiyun struct sprd_compr_stream *stream = runtime->private_data;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun memset(stream->info_area, 0, sizeof(struct sprd_compr_playinfo));
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun snd_compr_drain_notify(cstream);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
sprd_platform_compr_dma_complete(void * data)114*4882a593Smuzhiyun static void sprd_platform_compr_dma_complete(void *data)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun struct snd_compr_stream *cstream = data;
117*4882a593Smuzhiyun struct snd_compr_runtime *runtime = cstream->runtime;
118*4882a593Smuzhiyun struct sprd_compr_stream *stream = runtime->private_data;
119*4882a593Smuzhiyun struct sprd_compr_dma *dma = &stream->dma[1];
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* Update data size copied to IRAM buffer */
122*4882a593Smuzhiyun stream->copied_total += dma->trans_len;
123*4882a593Smuzhiyun if (stream->copied_total > stream->received_total)
124*4882a593Smuzhiyun stream->copied_total = stream->received_total;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun snd_compr_fragment_elapsed(cstream);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
sprd_platform_compr_dma_config(struct snd_soc_component * component,struct snd_compr_stream * cstream,struct snd_compr_params * params,int channel)129*4882a593Smuzhiyun static int sprd_platform_compr_dma_config(struct snd_soc_component *component,
130*4882a593Smuzhiyun struct snd_compr_stream *cstream,
131*4882a593Smuzhiyun struct snd_compr_params *params,
132*4882a593Smuzhiyun int channel)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct snd_compr_runtime *runtime = cstream->runtime;
135*4882a593Smuzhiyun struct sprd_compr_stream *stream = runtime->private_data;
136*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = cstream->private_data;
137*4882a593Smuzhiyun struct device *dev = component->dev;
138*4882a593Smuzhiyun struct sprd_compr_data *data = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
139*4882a593Smuzhiyun struct sprd_pcm_dma_params *dma_params = data->dma_params;
140*4882a593Smuzhiyun struct sprd_compr_dma *dma = &stream->dma[channel];
141*4882a593Smuzhiyun struct dma_slave_config config = { };
142*4882a593Smuzhiyun struct sprd_dma_linklist link = { };
143*4882a593Smuzhiyun enum dma_transfer_direction dir;
144*4882a593Smuzhiyun struct scatterlist *sg, *sgt;
145*4882a593Smuzhiyun enum dma_slave_buswidth bus_width;
146*4882a593Smuzhiyun int period, period_cnt, sg_num = 2;
147*4882a593Smuzhiyun dma_addr_t src_addr, dst_addr;
148*4882a593Smuzhiyun unsigned long flags;
149*4882a593Smuzhiyun int ret, j;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun if (!dma_params) {
152*4882a593Smuzhiyun dev_err(dev, "no dma parameters setting\n");
153*4882a593Smuzhiyun return -EINVAL;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun dma->chan = dma_request_slave_channel(dev,
157*4882a593Smuzhiyun dma_params->chan_name[channel]);
158*4882a593Smuzhiyun if (!dma->chan) {
159*4882a593Smuzhiyun dev_err(dev, "failed to request dma channel\n");
160*4882a593Smuzhiyun return -ENODEV;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun sgt = sg = devm_kcalloc(dev, sg_num, sizeof(*sg), GFP_KERNEL);
164*4882a593Smuzhiyun if (!sg) {
165*4882a593Smuzhiyun ret = -ENOMEM;
166*4882a593Smuzhiyun goto sg_err;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun switch (channel) {
170*4882a593Smuzhiyun case 0:
171*4882a593Smuzhiyun bus_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
172*4882a593Smuzhiyun period = (SPRD_COMPR_MCDT_FIFO_SIZE - SPRD_COMPR_MCDT_EMPTY_WMK) * 4;
173*4882a593Smuzhiyun period_cnt = params->buffer.fragment_size / period;
174*4882a593Smuzhiyun src_addr = stream->iram_buffer.addr;
175*4882a593Smuzhiyun dst_addr = dma_params->dev_phys[channel];
176*4882a593Smuzhiyun flags = SPRD_DMA_FLAGS(SPRD_DMA_SRC_CHN1,
177*4882a593Smuzhiyun SPRD_DMA_TRANS_DONE_TRG,
178*4882a593Smuzhiyun SPRD_DMA_FRAG_REQ,
179*4882a593Smuzhiyun SPRD_DMA_TRANS_INT);
180*4882a593Smuzhiyun break;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun case 1:
183*4882a593Smuzhiyun bus_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
184*4882a593Smuzhiyun period = params->buffer.fragment_size;
185*4882a593Smuzhiyun period_cnt = params->buffer.fragments;
186*4882a593Smuzhiyun src_addr = stream->compr_buffer.addr;
187*4882a593Smuzhiyun dst_addr = stream->iram_buffer.addr;
188*4882a593Smuzhiyun flags = SPRD_DMA_FLAGS(SPRD_DMA_DST_CHN1,
189*4882a593Smuzhiyun SPRD_DMA_TRANS_DONE_TRG,
190*4882a593Smuzhiyun SPRD_DMA_FRAG_REQ,
191*4882a593Smuzhiyun SPRD_DMA_TRANS_INT);
192*4882a593Smuzhiyun break;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun default:
195*4882a593Smuzhiyun ret = -EINVAL;
196*4882a593Smuzhiyun goto config_err;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun dma->trans_len = period * period_cnt;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun config.src_maxburst = period;
202*4882a593Smuzhiyun config.src_addr_width = bus_width;
203*4882a593Smuzhiyun config.dst_addr_width = bus_width;
204*4882a593Smuzhiyun if (cstream->direction == SND_COMPRESS_PLAYBACK) {
205*4882a593Smuzhiyun config.src_addr = src_addr;
206*4882a593Smuzhiyun config.dst_addr = dst_addr;
207*4882a593Smuzhiyun dir = DMA_MEM_TO_DEV;
208*4882a593Smuzhiyun } else {
209*4882a593Smuzhiyun config.src_addr = dst_addr;
210*4882a593Smuzhiyun config.dst_addr = src_addr;
211*4882a593Smuzhiyun dir = DMA_DEV_TO_MEM;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun sg_init_table(sgt, sg_num);
215*4882a593Smuzhiyun for (j = 0; j < sg_num; j++, sgt++) {
216*4882a593Smuzhiyun sg_dma_len(sgt) = dma->trans_len;
217*4882a593Smuzhiyun sg_dma_address(sgt) = dst_addr;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun /*
221*4882a593Smuzhiyun * Configure the link-list address for the DMA engine link-list
222*4882a593Smuzhiyun * mode.
223*4882a593Smuzhiyun */
224*4882a593Smuzhiyun link.virt_addr = (unsigned long)dma->virt;
225*4882a593Smuzhiyun link.phy_addr = dma->phys;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun ret = dmaengine_slave_config(dma->chan, &config);
228*4882a593Smuzhiyun if (ret) {
229*4882a593Smuzhiyun dev_err(dev,
230*4882a593Smuzhiyun "failed to set slave configuration: %d\n", ret);
231*4882a593Smuzhiyun goto config_err;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /*
235*4882a593Smuzhiyun * We configure the DMA request mode, interrupt mode, channel
236*4882a593Smuzhiyun * mode and channel trigger mode by the flags.
237*4882a593Smuzhiyun */
238*4882a593Smuzhiyun dma->desc = dma->chan->device->device_prep_slave_sg(dma->chan, sg,
239*4882a593Smuzhiyun sg_num, dir,
240*4882a593Smuzhiyun flags, &link);
241*4882a593Smuzhiyun if (!dma->desc) {
242*4882a593Smuzhiyun dev_err(dev, "failed to prepare slave sg\n");
243*4882a593Smuzhiyun ret = -ENOMEM;
244*4882a593Smuzhiyun goto config_err;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun /* Only channel 1 transfer can wake up the AP system. */
248*4882a593Smuzhiyun if (!params->no_wake_mode && channel == 1) {
249*4882a593Smuzhiyun dma->desc->callback = sprd_platform_compr_dma_complete;
250*4882a593Smuzhiyun dma->desc->callback_param = cstream;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun devm_kfree(dev, sg);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun return 0;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun config_err:
258*4882a593Smuzhiyun devm_kfree(dev, sg);
259*4882a593Smuzhiyun sg_err:
260*4882a593Smuzhiyun dma_release_channel(dma->chan);
261*4882a593Smuzhiyun return ret;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
sprd_platform_compr_set_params(struct snd_soc_component * component,struct snd_compr_stream * cstream,struct snd_compr_params * params)264*4882a593Smuzhiyun static int sprd_platform_compr_set_params(struct snd_soc_component *component,
265*4882a593Smuzhiyun struct snd_compr_stream *cstream,
266*4882a593Smuzhiyun struct snd_compr_params *params)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun struct snd_compr_runtime *runtime = cstream->runtime;
269*4882a593Smuzhiyun struct sprd_compr_stream *stream = runtime->private_data;
270*4882a593Smuzhiyun struct device *dev = component->dev;
271*4882a593Smuzhiyun struct sprd_compr_params compr_params = { };
272*4882a593Smuzhiyun int ret;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun /*
275*4882a593Smuzhiyun * Configure the DMA engine 2-stage transfer mode. Channel 1 set as the
276*4882a593Smuzhiyun * destination channel, and channel 0 set as the source channel, that
277*4882a593Smuzhiyun * means once the source channel's transaction is done, it will trigger
278*4882a593Smuzhiyun * the destination channel's transaction automatically.
279*4882a593Smuzhiyun */
280*4882a593Smuzhiyun ret = sprd_platform_compr_dma_config(component, cstream, params, 1);
281*4882a593Smuzhiyun if (ret) {
282*4882a593Smuzhiyun dev_err(dev, "failed to config stage 1 DMA: %d\n", ret);
283*4882a593Smuzhiyun return ret;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun ret = sprd_platform_compr_dma_config(component, cstream, params, 0);
287*4882a593Smuzhiyun if (ret) {
288*4882a593Smuzhiyun dev_err(dev, "failed to config stage 0 DMA: %d\n", ret);
289*4882a593Smuzhiyun goto config_err;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun compr_params.direction = cstream->direction;
293*4882a593Smuzhiyun compr_params.sample_rate = params->codec.sample_rate;
294*4882a593Smuzhiyun compr_params.channels = stream->num_channels;
295*4882a593Smuzhiyun compr_params.info_phys = stream->info_phys;
296*4882a593Smuzhiyun compr_params.info_size = stream->info_size;
297*4882a593Smuzhiyun compr_params.rate = params->codec.bit_rate;
298*4882a593Smuzhiyun compr_params.format = params->codec.id;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun ret = stream->compr_ops->set_params(cstream->direction, &compr_params);
301*4882a593Smuzhiyun if (ret) {
302*4882a593Smuzhiyun dev_err(dev, "failed to set parameters: %d\n", ret);
303*4882a593Smuzhiyun goto params_err;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun return 0;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun params_err:
309*4882a593Smuzhiyun dma_release_channel(stream->dma[0].chan);
310*4882a593Smuzhiyun config_err:
311*4882a593Smuzhiyun dma_release_channel(stream->dma[1].chan);
312*4882a593Smuzhiyun return ret;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
sprd_platform_compr_open(struct snd_soc_component * component,struct snd_compr_stream * cstream)315*4882a593Smuzhiyun static int sprd_platform_compr_open(struct snd_soc_component *component,
316*4882a593Smuzhiyun struct snd_compr_stream *cstream)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun struct snd_compr_runtime *runtime = cstream->runtime;
319*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = cstream->private_data;
320*4882a593Smuzhiyun struct device *dev = component->dev;
321*4882a593Smuzhiyun struct sprd_compr_data *data = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
322*4882a593Smuzhiyun struct sprd_compr_stream *stream;
323*4882a593Smuzhiyun struct sprd_compr_callback cb;
324*4882a593Smuzhiyun int stream_id = cstream->direction, ret;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
327*4882a593Smuzhiyun if (ret)
328*4882a593Smuzhiyun return ret;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun stream = devm_kzalloc(dev, sizeof(*stream), GFP_KERNEL);
331*4882a593Smuzhiyun if (!stream)
332*4882a593Smuzhiyun return -ENOMEM;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun stream->cstream = cstream;
335*4882a593Smuzhiyun stream->num_channels = 2;
336*4882a593Smuzhiyun stream->compr_ops = data->ops;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun /*
339*4882a593Smuzhiyun * Allocate the stage 0 IRAM buffer size, including the DMA 0
340*4882a593Smuzhiyun * link-list size and play information of DSP address size.
341*4882a593Smuzhiyun */
342*4882a593Smuzhiyun ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_IRAM, dev,
343*4882a593Smuzhiyun SPRD_COMPR_IRAM_SIZE, &stream->iram_buffer);
344*4882a593Smuzhiyun if (ret < 0)
345*4882a593Smuzhiyun goto err_iram;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun /* Use to save link-list configuration for DMA 0. */
348*4882a593Smuzhiyun stream->dma[0].virt = stream->iram_buffer.area + SPRD_COMPR_IRAM_SIZE;
349*4882a593Smuzhiyun stream->dma[0].phys = stream->iram_buffer.addr + SPRD_COMPR_IRAM_SIZE;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun /* Use to update the current data offset of DSP. */
352*4882a593Smuzhiyun stream->info_phys = stream->iram_buffer.addr + SPRD_COMPR_IRAM_SIZE +
353*4882a593Smuzhiyun SPRD_COMPR_IRAM_LINKLIST_SIZE;
354*4882a593Smuzhiyun stream->info_area = stream->iram_buffer.area + SPRD_COMPR_IRAM_SIZE +
355*4882a593Smuzhiyun SPRD_COMPR_IRAM_LINKLIST_SIZE;
356*4882a593Smuzhiyun stream->info_size = SPRD_COMPR_IRAM_INFO_SIZE;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun /*
359*4882a593Smuzhiyun * Allocate the stage 1 DDR buffer size, including the DMA 1 link-list
360*4882a593Smuzhiyun * size.
361*4882a593Smuzhiyun */
362*4882a593Smuzhiyun ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dev,
363*4882a593Smuzhiyun SPRD_COMPR_AREA_SIZE, &stream->compr_buffer);
364*4882a593Smuzhiyun if (ret < 0)
365*4882a593Smuzhiyun goto err_compr;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /* Use to save link-list configuration for DMA 1. */
368*4882a593Smuzhiyun stream->dma[1].virt = stream->compr_buffer.area + SPRD_COMPR_AREA_SIZE;
369*4882a593Smuzhiyun stream->dma[1].phys = stream->compr_buffer.addr + SPRD_COMPR_AREA_SIZE;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun cb.drain_notify = sprd_platform_compr_drain_notify;
372*4882a593Smuzhiyun cb.drain_data = cstream;
373*4882a593Smuzhiyun ret = stream->compr_ops->open(stream_id, &cb);
374*4882a593Smuzhiyun if (ret) {
375*4882a593Smuzhiyun dev_err(dev, "failed to open compress platform: %d\n", ret);
376*4882a593Smuzhiyun goto err_open;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun runtime->private_data = stream;
380*4882a593Smuzhiyun return 0;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun err_open:
383*4882a593Smuzhiyun snd_dma_free_pages(&stream->compr_buffer);
384*4882a593Smuzhiyun err_compr:
385*4882a593Smuzhiyun snd_dma_free_pages(&stream->iram_buffer);
386*4882a593Smuzhiyun err_iram:
387*4882a593Smuzhiyun devm_kfree(dev, stream);
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun return ret;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
sprd_platform_compr_free(struct snd_soc_component * component,struct snd_compr_stream * cstream)392*4882a593Smuzhiyun static int sprd_platform_compr_free(struct snd_soc_component *component,
393*4882a593Smuzhiyun struct snd_compr_stream *cstream)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun struct snd_compr_runtime *runtime = cstream->runtime;
396*4882a593Smuzhiyun struct sprd_compr_stream *stream = runtime->private_data;
397*4882a593Smuzhiyun struct device *dev = component->dev;
398*4882a593Smuzhiyun int stream_id = cstream->direction, i;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun for (i = 0; i < stream->num_channels; i++) {
401*4882a593Smuzhiyun struct sprd_compr_dma *dma = &stream->dma[i];
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun if (dma->chan) {
404*4882a593Smuzhiyun dma_release_channel(dma->chan);
405*4882a593Smuzhiyun dma->chan = NULL;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun snd_dma_free_pages(&stream->compr_buffer);
410*4882a593Smuzhiyun snd_dma_free_pages(&stream->iram_buffer);
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun stream->compr_ops->close(stream_id);
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun devm_kfree(dev, stream);
415*4882a593Smuzhiyun return 0;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
sprd_platform_compr_trigger(struct snd_soc_component * component,struct snd_compr_stream * cstream,int cmd)418*4882a593Smuzhiyun static int sprd_platform_compr_trigger(struct snd_soc_component *component,
419*4882a593Smuzhiyun struct snd_compr_stream *cstream,
420*4882a593Smuzhiyun int cmd)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun struct snd_compr_runtime *runtime = cstream->runtime;
423*4882a593Smuzhiyun struct sprd_compr_stream *stream = runtime->private_data;
424*4882a593Smuzhiyun struct device *dev = component->dev;
425*4882a593Smuzhiyun int channels = stream->num_channels, ret = 0, i;
426*4882a593Smuzhiyun int stream_id = cstream->direction;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (cstream->direction != SND_COMPRESS_PLAYBACK) {
429*4882a593Smuzhiyun dev_err(dev, "unsupported compress direction\n");
430*4882a593Smuzhiyun return -EINVAL;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun switch (cmd) {
434*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
435*4882a593Smuzhiyun for (i = channels - 1; i >= 0; i--) {
436*4882a593Smuzhiyun struct sprd_compr_dma *dma = &stream->dma[i];
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun if (!dma->desc)
439*4882a593Smuzhiyun continue;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun dma->cookie = dmaengine_submit(dma->desc);
442*4882a593Smuzhiyun ret = dma_submit_error(dma->cookie);
443*4882a593Smuzhiyun if (ret) {
444*4882a593Smuzhiyun dev_err(dev, "failed to submit request: %d\n",
445*4882a593Smuzhiyun ret);
446*4882a593Smuzhiyun return ret;
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun for (i = channels - 1; i >= 0; i--) {
451*4882a593Smuzhiyun struct sprd_compr_dma *dma = &stream->dma[i];
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun if (dma->chan)
454*4882a593Smuzhiyun dma_async_issue_pending(dma->chan);
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun ret = stream->compr_ops->start(stream_id);
458*4882a593Smuzhiyun break;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
461*4882a593Smuzhiyun for (i = channels - 1; i >= 0; i--) {
462*4882a593Smuzhiyun struct sprd_compr_dma *dma = &stream->dma[i];
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun if (dma->chan)
465*4882a593Smuzhiyun dmaengine_terminate_async(dma->chan);
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun stream->copied_total = 0;
469*4882a593Smuzhiyun stream->stage1_pointer = 0;
470*4882a593Smuzhiyun stream->received_total = 0;
471*4882a593Smuzhiyun stream->received_stage0 = 0;
472*4882a593Smuzhiyun stream->received_stage1 = 0;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun ret = stream->compr_ops->stop(stream_id);
475*4882a593Smuzhiyun break;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
478*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
479*4882a593Smuzhiyun for (i = channels - 1; i >= 0; i--) {
480*4882a593Smuzhiyun struct sprd_compr_dma *dma = &stream->dma[i];
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun if (dma->chan)
483*4882a593Smuzhiyun dmaengine_pause(dma->chan);
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun ret = stream->compr_ops->pause(stream_id);
487*4882a593Smuzhiyun break;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
490*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
491*4882a593Smuzhiyun for (i = channels - 1; i >= 0; i--) {
492*4882a593Smuzhiyun struct sprd_compr_dma *dma = &stream->dma[i];
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun if (dma->chan)
495*4882a593Smuzhiyun dmaengine_resume(dma->chan);
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun ret = stream->compr_ops->pause_release(stream_id);
499*4882a593Smuzhiyun break;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun case SND_COMPR_TRIGGER_PARTIAL_DRAIN:
502*4882a593Smuzhiyun case SND_COMPR_TRIGGER_DRAIN:
503*4882a593Smuzhiyun ret = stream->compr_ops->drain(stream->received_total);
504*4882a593Smuzhiyun break;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun default:
507*4882a593Smuzhiyun ret = -EINVAL;
508*4882a593Smuzhiyun break;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun return ret;
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
sprd_platform_compr_pointer(struct snd_soc_component * component,struct snd_compr_stream * cstream,struct snd_compr_tstamp * tstamp)514*4882a593Smuzhiyun static int sprd_platform_compr_pointer(struct snd_soc_component *component,
515*4882a593Smuzhiyun struct snd_compr_stream *cstream,
516*4882a593Smuzhiyun struct snd_compr_tstamp *tstamp)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun struct snd_compr_runtime *runtime = cstream->runtime;
519*4882a593Smuzhiyun struct sprd_compr_stream *stream = runtime->private_data;
520*4882a593Smuzhiyun struct sprd_compr_playinfo *info =
521*4882a593Smuzhiyun (struct sprd_compr_playinfo *)stream->info_area;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun tstamp->copied_total = stream->copied_total;
524*4882a593Smuzhiyun tstamp->pcm_io_frames = info->current_data_offset;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun return 0;
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
sprd_platform_compr_copy(struct snd_soc_component * component,struct snd_compr_stream * cstream,char __user * buf,size_t count)529*4882a593Smuzhiyun static int sprd_platform_compr_copy(struct snd_soc_component *component,
530*4882a593Smuzhiyun struct snd_compr_stream *cstream,
531*4882a593Smuzhiyun char __user *buf, size_t count)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun struct snd_compr_runtime *runtime = cstream->runtime;
534*4882a593Smuzhiyun struct sprd_compr_stream *stream = runtime->private_data;
535*4882a593Smuzhiyun int avail_bytes, data_count = count;
536*4882a593Smuzhiyun void *dst;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun /*
539*4882a593Smuzhiyun * We usually set fragment size as 32K, and the stage 0 IRAM buffer
540*4882a593Smuzhiyun * size is 32K too. So if now the received data size of the stage 0
541*4882a593Smuzhiyun * IRAM buffer is less than 32K, that means we have some available
542*4882a593Smuzhiyun * spaces for the stage 0 IRAM buffer.
543*4882a593Smuzhiyun */
544*4882a593Smuzhiyun if (stream->received_stage0 < runtime->fragment_size) {
545*4882a593Smuzhiyun avail_bytes = runtime->fragment_size - stream->received_stage0;
546*4882a593Smuzhiyun dst = stream->iram_buffer.area + stream->received_stage0;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun if (avail_bytes >= data_count) {
549*4882a593Smuzhiyun /*
550*4882a593Smuzhiyun * Copy data to the stage 0 IRAM buffer directly if
551*4882a593Smuzhiyun * spaces are enough.
552*4882a593Smuzhiyun */
553*4882a593Smuzhiyun if (copy_from_user(dst, buf, data_count))
554*4882a593Smuzhiyun return -EFAULT;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun stream->received_stage0 += data_count;
557*4882a593Smuzhiyun stream->copied_total += data_count;
558*4882a593Smuzhiyun goto copy_done;
559*4882a593Smuzhiyun } else {
560*4882a593Smuzhiyun /*
561*4882a593Smuzhiyun * If the data count is larger than the available spaces
562*4882a593Smuzhiyun * of the stage 0 IRAM buffer, we should copy one
563*4882a593Smuzhiyun * partial data to the stage 0 IRAM buffer, and copy
564*4882a593Smuzhiyun * the left to the stage 1 DDR buffer.
565*4882a593Smuzhiyun */
566*4882a593Smuzhiyun if (copy_from_user(dst, buf, avail_bytes))
567*4882a593Smuzhiyun return -EFAULT;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun data_count -= avail_bytes;
570*4882a593Smuzhiyun stream->received_stage0 += avail_bytes;
571*4882a593Smuzhiyun stream->copied_total += avail_bytes;
572*4882a593Smuzhiyun buf += avail_bytes;
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun /*
577*4882a593Smuzhiyun * Copy data to the stage 1 DDR buffer if no spaces for the stage 0 IRAM
578*4882a593Smuzhiyun * buffer.
579*4882a593Smuzhiyun */
580*4882a593Smuzhiyun dst = stream->compr_buffer.area + stream->stage1_pointer;
581*4882a593Smuzhiyun if (data_count < stream->compr_buffer.bytes - stream->stage1_pointer) {
582*4882a593Smuzhiyun if (copy_from_user(dst, buf, data_count))
583*4882a593Smuzhiyun return -EFAULT;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun stream->stage1_pointer += data_count;
586*4882a593Smuzhiyun } else {
587*4882a593Smuzhiyun avail_bytes = stream->compr_buffer.bytes - stream->stage1_pointer;
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun if (copy_from_user(dst, buf, avail_bytes))
590*4882a593Smuzhiyun return -EFAULT;
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun if (copy_from_user(stream->compr_buffer.area, buf + avail_bytes,
593*4882a593Smuzhiyun data_count - avail_bytes))
594*4882a593Smuzhiyun return -EFAULT;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun stream->stage1_pointer = data_count - avail_bytes;
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun stream->received_stage1 += data_count;
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun copy_done:
602*4882a593Smuzhiyun /* Update the copied data size. */
603*4882a593Smuzhiyun stream->received_total += count;
604*4882a593Smuzhiyun return count;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
sprd_platform_compr_get_caps(struct snd_soc_component * component,struct snd_compr_stream * cstream,struct snd_compr_caps * caps)607*4882a593Smuzhiyun static int sprd_platform_compr_get_caps(struct snd_soc_component *component,
608*4882a593Smuzhiyun struct snd_compr_stream *cstream,
609*4882a593Smuzhiyun struct snd_compr_caps *caps)
610*4882a593Smuzhiyun {
611*4882a593Smuzhiyun caps->direction = cstream->direction;
612*4882a593Smuzhiyun caps->min_fragment_size = SPRD_COMPR_MIN_FRAGMENT_SIZE;
613*4882a593Smuzhiyun caps->max_fragment_size = SPRD_COMPR_MAX_FRAGMENT_SIZE;
614*4882a593Smuzhiyun caps->min_fragments = SPRD_COMPR_MIN_NUM_FRAGMENTS;
615*4882a593Smuzhiyun caps->max_fragments = SPRD_COMPR_MAX_NUM_FRAGMENTS;
616*4882a593Smuzhiyun caps->num_codecs = 2;
617*4882a593Smuzhiyun caps->codecs[0] = SND_AUDIOCODEC_MP3;
618*4882a593Smuzhiyun caps->codecs[1] = SND_AUDIOCODEC_AAC;
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun return 0;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun static int
sprd_platform_compr_get_codec_caps(struct snd_soc_component * component,struct snd_compr_stream * cstream,struct snd_compr_codec_caps * codec)624*4882a593Smuzhiyun sprd_platform_compr_get_codec_caps(struct snd_soc_component *component,
625*4882a593Smuzhiyun struct snd_compr_stream *cstream,
626*4882a593Smuzhiyun struct snd_compr_codec_caps *codec)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun switch (codec->codec) {
629*4882a593Smuzhiyun case SND_AUDIOCODEC_MP3:
630*4882a593Smuzhiyun codec->num_descriptors = 2;
631*4882a593Smuzhiyun codec->descriptor[0].max_ch = 2;
632*4882a593Smuzhiyun codec->descriptor[0].bit_rate[0] = 320;
633*4882a593Smuzhiyun codec->descriptor[0].bit_rate[1] = 128;
634*4882a593Smuzhiyun codec->descriptor[0].num_bitrates = 2;
635*4882a593Smuzhiyun codec->descriptor[0].profiles = 0;
636*4882a593Smuzhiyun codec->descriptor[0].modes = SND_AUDIOCHANMODE_MP3_STEREO;
637*4882a593Smuzhiyun codec->descriptor[0].formats = 0;
638*4882a593Smuzhiyun break;
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun case SND_AUDIOCODEC_AAC:
641*4882a593Smuzhiyun codec->num_descriptors = 2;
642*4882a593Smuzhiyun codec->descriptor[1].max_ch = 2;
643*4882a593Smuzhiyun codec->descriptor[1].bit_rate[0] = 320;
644*4882a593Smuzhiyun codec->descriptor[1].bit_rate[1] = 128;
645*4882a593Smuzhiyun codec->descriptor[1].num_bitrates = 2;
646*4882a593Smuzhiyun codec->descriptor[1].profiles = 0;
647*4882a593Smuzhiyun codec->descriptor[1].modes = 0;
648*4882a593Smuzhiyun codec->descriptor[1].formats = 0;
649*4882a593Smuzhiyun break;
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun default:
652*4882a593Smuzhiyun return -EINVAL;
653*4882a593Smuzhiyun }
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun return 0;
656*4882a593Smuzhiyun }
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun const struct snd_compress_ops sprd_platform_compress_ops = {
659*4882a593Smuzhiyun .open = sprd_platform_compr_open,
660*4882a593Smuzhiyun .free = sprd_platform_compr_free,
661*4882a593Smuzhiyun .set_params = sprd_platform_compr_set_params,
662*4882a593Smuzhiyun .trigger = sprd_platform_compr_trigger,
663*4882a593Smuzhiyun .pointer = sprd_platform_compr_pointer,
664*4882a593Smuzhiyun .copy = sprd_platform_compr_copy,
665*4882a593Smuzhiyun .get_caps = sprd_platform_compr_get_caps,
666*4882a593Smuzhiyun .get_codec_caps = sprd_platform_compr_get_codec_caps,
667*4882a593Smuzhiyun };
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun MODULE_DESCRIPTION("Spreadtrum ASoC Compress Platform Driver");
670*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
671*4882a593Smuzhiyun MODULE_ALIAS("platform:compress-platform");
672