xref: /OK3568_Linux_fs/kernel/sound/soc/sof/sof-priv.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * This file is provided under a dual BSD/GPLv2 license.  When using or
4*4882a593Smuzhiyun  * redistributing this file, you may do so under either license.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright(c) 2018 Intel Corporation. All rights reserved.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #ifndef __SOUND_SOC_SOF_PRIV_H
12*4882a593Smuzhiyun #define __SOUND_SOC_SOF_PRIV_H
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/device.h>
15*4882a593Smuzhiyun #include <sound/hdaudio.h>
16*4882a593Smuzhiyun #include <sound/sof.h>
17*4882a593Smuzhiyun #include <sound/sof/info.h>
18*4882a593Smuzhiyun #include <sound/sof/pm.h>
19*4882a593Smuzhiyun #include <sound/sof/trace.h>
20*4882a593Smuzhiyun #include <uapi/sound/sof/fw.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* debug flags */
23*4882a593Smuzhiyun #define SOF_DBG_ENABLE_TRACE	BIT(0)
24*4882a593Smuzhiyun #define SOF_DBG_REGS		BIT(1)
25*4882a593Smuzhiyun #define SOF_DBG_MBOX		BIT(2)
26*4882a593Smuzhiyun #define SOF_DBG_TEXT		BIT(3)
27*4882a593Smuzhiyun #define SOF_DBG_PCI		BIT(4)
28*4882a593Smuzhiyun #define SOF_DBG_RETAIN_CTX	BIT(5)	/* prevent DSP D3 on FW exception */
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /* global debug state set by SOF_DBG_ flags */
31*4882a593Smuzhiyun extern int sof_core_debug;
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* max BARs mmaped devices can use */
34*4882a593Smuzhiyun #define SND_SOF_BARS	8
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /* time in ms for runtime suspend delay */
37*4882a593Smuzhiyun #define SND_SOF_SUSPEND_DELAY_MS	2000
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /* DMA buffer size for trace */
40*4882a593Smuzhiyun #define DMA_BUF_SIZE_FOR_TRACE (PAGE_SIZE * 16)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define SOF_IPC_DSP_REPLY		0
43*4882a593Smuzhiyun #define SOF_IPC_HOST_REPLY		1
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* convenience constructor for DAI driver streams */
46*4882a593Smuzhiyun #define SOF_DAI_STREAM(sname, scmin, scmax, srates, sfmt) \
47*4882a593Smuzhiyun 	{.stream_name = sname, .channels_min = scmin, .channels_max = scmax, \
48*4882a593Smuzhiyun 	 .rates = srates, .formats = sfmt}
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define SOF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
51*4882a593Smuzhiyun 	SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_FLOAT)
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define ENABLE_DEBUGFS_CACHEBUF \
54*4882a593Smuzhiyun 	(IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE) || \
55*4882a593Smuzhiyun 	 IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST))
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun /* So far the primary core on all DSPs has ID 0 */
58*4882a593Smuzhiyun #define SOF_DSP_PRIMARY_CORE 0
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /* DSP power state */
61*4882a593Smuzhiyun enum sof_dsp_power_states {
62*4882a593Smuzhiyun 	SOF_DSP_PM_D0,
63*4882a593Smuzhiyun 	SOF_DSP_PM_D1,
64*4882a593Smuzhiyun 	SOF_DSP_PM_D2,
65*4882a593Smuzhiyun 	SOF_DSP_PM_D3_HOT,
66*4882a593Smuzhiyun 	SOF_DSP_PM_D3,
67*4882a593Smuzhiyun 	SOF_DSP_PM_D3_COLD,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun struct sof_dsp_power_state {
71*4882a593Smuzhiyun 	u32 state;
72*4882a593Smuzhiyun 	u32 substate; /* platform-specific */
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* System suspend target state */
76*4882a593Smuzhiyun enum sof_system_suspend_state {
77*4882a593Smuzhiyun 	SOF_SUSPEND_NONE = 0,
78*4882a593Smuzhiyun 	SOF_SUSPEND_S0IX,
79*4882a593Smuzhiyun 	SOF_SUSPEND_S3,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun struct snd_sof_dev;
83*4882a593Smuzhiyun struct snd_sof_ipc_msg;
84*4882a593Smuzhiyun struct snd_sof_ipc;
85*4882a593Smuzhiyun struct snd_sof_debugfs_map;
86*4882a593Smuzhiyun struct snd_soc_tplg_ops;
87*4882a593Smuzhiyun struct snd_soc_component;
88*4882a593Smuzhiyun struct snd_sof_pdata;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun  * SOF DSP HW abstraction operations.
92*4882a593Smuzhiyun  * Used to abstract DSP HW architecture and any IO busses between host CPU
93*4882a593Smuzhiyun  * and DSP device(s).
94*4882a593Smuzhiyun  */
95*4882a593Smuzhiyun struct snd_sof_dsp_ops {
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	/* probe and remove */
98*4882a593Smuzhiyun 	int (*probe)(struct snd_sof_dev *sof_dev); /* mandatory */
99*4882a593Smuzhiyun 	int (*remove)(struct snd_sof_dev *sof_dev); /* optional */
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	/* DSP core boot / reset */
102*4882a593Smuzhiyun 	int (*run)(struct snd_sof_dev *sof_dev); /* mandatory */
103*4882a593Smuzhiyun 	int (*stall)(struct snd_sof_dev *sof_dev); /* optional */
104*4882a593Smuzhiyun 	int (*reset)(struct snd_sof_dev *sof_dev); /* optional */
105*4882a593Smuzhiyun 	int (*core_power_up)(struct snd_sof_dev *sof_dev,
106*4882a593Smuzhiyun 			     unsigned int core_mask); /* optional */
107*4882a593Smuzhiyun 	int (*core_power_down)(struct snd_sof_dev *sof_dev,
108*4882a593Smuzhiyun 			       unsigned int core_mask); /* optional */
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	/*
111*4882a593Smuzhiyun 	 * Register IO: only used by respective drivers themselves,
112*4882a593Smuzhiyun 	 * TODO: consider removing these operations and calling respective
113*4882a593Smuzhiyun 	 * implementations directly
114*4882a593Smuzhiyun 	 */
115*4882a593Smuzhiyun 	void (*write)(struct snd_sof_dev *sof_dev, void __iomem *addr,
116*4882a593Smuzhiyun 		      u32 value); /* optional */
117*4882a593Smuzhiyun 	u32 (*read)(struct snd_sof_dev *sof_dev,
118*4882a593Smuzhiyun 		    void __iomem *addr); /* optional */
119*4882a593Smuzhiyun 	void (*write64)(struct snd_sof_dev *sof_dev, void __iomem *addr,
120*4882a593Smuzhiyun 			u64 value); /* optional */
121*4882a593Smuzhiyun 	u64 (*read64)(struct snd_sof_dev *sof_dev,
122*4882a593Smuzhiyun 		      void __iomem *addr); /* optional */
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/* memcpy IO */
125*4882a593Smuzhiyun 	void (*block_read)(struct snd_sof_dev *sof_dev, u32 bar,
126*4882a593Smuzhiyun 			   u32 offset, void *dest,
127*4882a593Smuzhiyun 			   size_t size); /* mandatory */
128*4882a593Smuzhiyun 	void (*block_write)(struct snd_sof_dev *sof_dev, u32 bar,
129*4882a593Smuzhiyun 			    u32 offset, void *src,
130*4882a593Smuzhiyun 			    size_t size); /* mandatory */
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	/* doorbell */
133*4882a593Smuzhiyun 	irqreturn_t (*irq_handler)(int irq, void *context); /* optional */
134*4882a593Smuzhiyun 	irqreturn_t (*irq_thread)(int irq, void *context); /* optional */
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	/* ipc */
137*4882a593Smuzhiyun 	int (*send_msg)(struct snd_sof_dev *sof_dev,
138*4882a593Smuzhiyun 			struct snd_sof_ipc_msg *msg); /* mandatory */
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	/* FW loading */
141*4882a593Smuzhiyun 	int (*load_firmware)(struct snd_sof_dev *sof_dev); /* mandatory */
142*4882a593Smuzhiyun 	int (*load_module)(struct snd_sof_dev *sof_dev,
143*4882a593Smuzhiyun 			   struct snd_sof_mod_hdr *hdr); /* optional */
144*4882a593Smuzhiyun 	/*
145*4882a593Smuzhiyun 	 * FW ready checks for ABI compatibility and creates
146*4882a593Smuzhiyun 	 * memory windows at first boot
147*4882a593Smuzhiyun 	 */
148*4882a593Smuzhiyun 	int (*fw_ready)(struct snd_sof_dev *sdev, u32 msg_id); /* mandatory */
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	/* connect pcm substream to a host stream */
151*4882a593Smuzhiyun 	int (*pcm_open)(struct snd_sof_dev *sdev,
152*4882a593Smuzhiyun 			struct snd_pcm_substream *substream); /* optional */
153*4882a593Smuzhiyun 	/* disconnect pcm substream to a host stream */
154*4882a593Smuzhiyun 	int (*pcm_close)(struct snd_sof_dev *sdev,
155*4882a593Smuzhiyun 			 struct snd_pcm_substream *substream); /* optional */
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/* host stream hw params */
158*4882a593Smuzhiyun 	int (*pcm_hw_params)(struct snd_sof_dev *sdev,
159*4882a593Smuzhiyun 			     struct snd_pcm_substream *substream,
160*4882a593Smuzhiyun 			     struct snd_pcm_hw_params *params,
161*4882a593Smuzhiyun 			     struct sof_ipc_stream_params *ipc_params); /* optional */
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	/* host stream hw_free */
164*4882a593Smuzhiyun 	int (*pcm_hw_free)(struct snd_sof_dev *sdev,
165*4882a593Smuzhiyun 			   struct snd_pcm_substream *substream); /* optional */
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	/* host stream trigger */
168*4882a593Smuzhiyun 	int (*pcm_trigger)(struct snd_sof_dev *sdev,
169*4882a593Smuzhiyun 			   struct snd_pcm_substream *substream,
170*4882a593Smuzhiyun 			   int cmd); /* optional */
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	/* host stream pointer */
173*4882a593Smuzhiyun 	snd_pcm_uframes_t (*pcm_pointer)(struct snd_sof_dev *sdev,
174*4882a593Smuzhiyun 					 struct snd_pcm_substream *substream); /* optional */
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_PROBES)
177*4882a593Smuzhiyun 	/* Except for probe_pointer, all probe ops are mandatory */
178*4882a593Smuzhiyun 	int (*probe_assign)(struct snd_sof_dev *sdev,
179*4882a593Smuzhiyun 			struct snd_compr_stream *cstream,
180*4882a593Smuzhiyun 			struct snd_soc_dai *dai); /* mandatory */
181*4882a593Smuzhiyun 	int (*probe_free)(struct snd_sof_dev *sdev,
182*4882a593Smuzhiyun 			struct snd_compr_stream *cstream,
183*4882a593Smuzhiyun 			struct snd_soc_dai *dai); /* mandatory */
184*4882a593Smuzhiyun 	int (*probe_set_params)(struct snd_sof_dev *sdev,
185*4882a593Smuzhiyun 			struct snd_compr_stream *cstream,
186*4882a593Smuzhiyun 			struct snd_compr_params *params,
187*4882a593Smuzhiyun 			struct snd_soc_dai *dai); /* mandatory */
188*4882a593Smuzhiyun 	int (*probe_trigger)(struct snd_sof_dev *sdev,
189*4882a593Smuzhiyun 			struct snd_compr_stream *cstream, int cmd,
190*4882a593Smuzhiyun 			struct snd_soc_dai *dai); /* mandatory */
191*4882a593Smuzhiyun 	int (*probe_pointer)(struct snd_sof_dev *sdev,
192*4882a593Smuzhiyun 			struct snd_compr_stream *cstream,
193*4882a593Smuzhiyun 			struct snd_compr_tstamp *tstamp,
194*4882a593Smuzhiyun 			struct snd_soc_dai *dai); /* optional */
195*4882a593Smuzhiyun #endif
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	/* host read DSP stream data */
198*4882a593Smuzhiyun 	void (*ipc_msg_data)(struct snd_sof_dev *sdev,
199*4882a593Smuzhiyun 			     struct snd_pcm_substream *substream,
200*4882a593Smuzhiyun 			     void *p, size_t sz); /* mandatory */
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	/* host configure DSP HW parameters */
203*4882a593Smuzhiyun 	int (*ipc_pcm_params)(struct snd_sof_dev *sdev,
204*4882a593Smuzhiyun 			      struct snd_pcm_substream *substream,
205*4882a593Smuzhiyun 			      const struct sof_ipc_pcm_params_reply *reply); /* mandatory */
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* pre/post firmware run */
208*4882a593Smuzhiyun 	int (*pre_fw_run)(struct snd_sof_dev *sof_dev); /* optional */
209*4882a593Smuzhiyun 	int (*post_fw_run)(struct snd_sof_dev *sof_dev); /* optional */
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	/* DSP PM */
212*4882a593Smuzhiyun 	int (*suspend)(struct snd_sof_dev *sof_dev,
213*4882a593Smuzhiyun 		       u32 target_state); /* optional */
214*4882a593Smuzhiyun 	int (*resume)(struct snd_sof_dev *sof_dev); /* optional */
215*4882a593Smuzhiyun 	int (*runtime_suspend)(struct snd_sof_dev *sof_dev); /* optional */
216*4882a593Smuzhiyun 	int (*runtime_resume)(struct snd_sof_dev *sof_dev); /* optional */
217*4882a593Smuzhiyun 	int (*runtime_idle)(struct snd_sof_dev *sof_dev); /* optional */
218*4882a593Smuzhiyun 	int (*set_hw_params_upon_resume)(struct snd_sof_dev *sdev); /* optional */
219*4882a593Smuzhiyun 	int (*set_power_state)(struct snd_sof_dev *sdev,
220*4882a593Smuzhiyun 			       const struct sof_dsp_power_state *target_state); /* optional */
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	/* DSP clocking */
223*4882a593Smuzhiyun 	int (*set_clk)(struct snd_sof_dev *sof_dev, u32 freq); /* optional */
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	/* debug */
226*4882a593Smuzhiyun 	const struct snd_sof_debugfs_map *debug_map; /* optional */
227*4882a593Smuzhiyun 	int debug_map_count; /* optional */
228*4882a593Smuzhiyun 	void (*dbg_dump)(struct snd_sof_dev *sof_dev,
229*4882a593Smuzhiyun 			 u32 flags); /* optional */
230*4882a593Smuzhiyun 	void (*ipc_dump)(struct snd_sof_dev *sof_dev); /* optional */
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	/* host DMA trace initialization */
233*4882a593Smuzhiyun 	int (*trace_init)(struct snd_sof_dev *sdev,
234*4882a593Smuzhiyun 			  u32 *stream_tag); /* optional */
235*4882a593Smuzhiyun 	int (*trace_release)(struct snd_sof_dev *sdev); /* optional */
236*4882a593Smuzhiyun 	int (*trace_trigger)(struct snd_sof_dev *sdev,
237*4882a593Smuzhiyun 			     int cmd); /* optional */
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	/* misc */
240*4882a593Smuzhiyun 	int (*get_bar_index)(struct snd_sof_dev *sdev,
241*4882a593Smuzhiyun 			     u32 type); /* optional */
242*4882a593Smuzhiyun 	int (*get_mailbox_offset)(struct snd_sof_dev *sdev);/* mandatory for common loader code */
243*4882a593Smuzhiyun 	int (*get_window_offset)(struct snd_sof_dev *sdev,
244*4882a593Smuzhiyun 				 u32 id);/* mandatory for common loader code */
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	/* machine driver ops */
247*4882a593Smuzhiyun 	int (*machine_register)(struct snd_sof_dev *sdev,
248*4882a593Smuzhiyun 				void *pdata); /* optional */
249*4882a593Smuzhiyun 	void (*machine_unregister)(struct snd_sof_dev *sdev,
250*4882a593Smuzhiyun 				   void *pdata); /* optional */
251*4882a593Smuzhiyun 	void (*machine_select)(struct snd_sof_dev *sdev); /* optional */
252*4882a593Smuzhiyun 	void (*set_mach_params)(const struct snd_soc_acpi_mach *mach,
253*4882a593Smuzhiyun 				struct device *dev); /* optional */
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	/* DAI ops */
256*4882a593Smuzhiyun 	struct snd_soc_dai_driver *drv;
257*4882a593Smuzhiyun 	int num_drv;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	/* ALSA HW info flags, will be stored in snd_pcm_runtime.hw.info */
260*4882a593Smuzhiyun 	u32 hw_info;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	const struct sof_arch_ops *arch_ops;
263*4882a593Smuzhiyun };
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun /* DSP architecture specific callbacks for oops and stack dumps */
266*4882a593Smuzhiyun struct sof_arch_ops {
267*4882a593Smuzhiyun 	void (*dsp_oops)(struct snd_sof_dev *sdev, void *oops);
268*4882a593Smuzhiyun 	void (*dsp_stack)(struct snd_sof_dev *sdev, void *oops,
269*4882a593Smuzhiyun 			  u32 *stack, u32 stack_words);
270*4882a593Smuzhiyun };
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun #define sof_arch_ops(sdev) ((sdev)->pdata->desc->ops->arch_ops)
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun /* DSP device HW descriptor mapping between bus ID and ops */
275*4882a593Smuzhiyun struct sof_ops_table {
276*4882a593Smuzhiyun 	const struct sof_dev_desc *desc;
277*4882a593Smuzhiyun 	const struct snd_sof_dsp_ops *ops;
278*4882a593Smuzhiyun };
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun enum sof_dfsentry_type {
281*4882a593Smuzhiyun 	SOF_DFSENTRY_TYPE_IOMEM = 0,
282*4882a593Smuzhiyun 	SOF_DFSENTRY_TYPE_BUF,
283*4882a593Smuzhiyun };
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun enum sof_debugfs_access_type {
286*4882a593Smuzhiyun 	SOF_DEBUGFS_ACCESS_ALWAYS = 0,
287*4882a593Smuzhiyun 	SOF_DEBUGFS_ACCESS_D0_ONLY,
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun /* FS entry for debug files that can expose DSP memories, registers */
291*4882a593Smuzhiyun struct snd_sof_dfsentry {
292*4882a593Smuzhiyun 	size_t size;
293*4882a593Smuzhiyun 	enum sof_dfsentry_type type;
294*4882a593Smuzhiyun 	/*
295*4882a593Smuzhiyun 	 * access_type specifies if the
296*4882a593Smuzhiyun 	 * memory -> DSP resource (memory, register etc) is always accessible
297*4882a593Smuzhiyun 	 * or if it is accessible only when the DSP is in D0.
298*4882a593Smuzhiyun 	 */
299*4882a593Smuzhiyun 	enum sof_debugfs_access_type access_type;
300*4882a593Smuzhiyun #if ENABLE_DEBUGFS_CACHEBUF
301*4882a593Smuzhiyun 	char *cache_buf; /* buffer to cache the contents of debugfs memory */
302*4882a593Smuzhiyun #endif
303*4882a593Smuzhiyun 	struct snd_sof_dev *sdev;
304*4882a593Smuzhiyun 	struct list_head list;  /* list in sdev dfsentry list */
305*4882a593Smuzhiyun 	union {
306*4882a593Smuzhiyun 		void __iomem *io_mem;
307*4882a593Smuzhiyun 		void *buf;
308*4882a593Smuzhiyun 	};
309*4882a593Smuzhiyun };
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun /* Debug mapping for any DSP memory or registers that can used for debug */
312*4882a593Smuzhiyun struct snd_sof_debugfs_map {
313*4882a593Smuzhiyun 	const char *name;
314*4882a593Smuzhiyun 	u32 bar;
315*4882a593Smuzhiyun 	u32 offset;
316*4882a593Smuzhiyun 	u32 size;
317*4882a593Smuzhiyun 	/*
318*4882a593Smuzhiyun 	 * access_type specifies if the memory is always accessible
319*4882a593Smuzhiyun 	 * or if it is accessible only when the DSP is in D0.
320*4882a593Smuzhiyun 	 */
321*4882a593Smuzhiyun 	enum sof_debugfs_access_type access_type;
322*4882a593Smuzhiyun };
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun /* mailbox descriptor, used for host <-> DSP IPC */
325*4882a593Smuzhiyun struct snd_sof_mailbox {
326*4882a593Smuzhiyun 	u32 offset;
327*4882a593Smuzhiyun 	size_t size;
328*4882a593Smuzhiyun };
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun /* IPC message descriptor for host <-> DSP IO */
331*4882a593Smuzhiyun struct snd_sof_ipc_msg {
332*4882a593Smuzhiyun 	/* message data */
333*4882a593Smuzhiyun 	u32 header;
334*4882a593Smuzhiyun 	void *msg_data;
335*4882a593Smuzhiyun 	void *reply_data;
336*4882a593Smuzhiyun 	size_t msg_size;
337*4882a593Smuzhiyun 	size_t reply_size;
338*4882a593Smuzhiyun 	int reply_error;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	wait_queue_head_t waitq;
341*4882a593Smuzhiyun 	bool ipc_complete;
342*4882a593Smuzhiyun };
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun enum snd_sof_fw_state {
345*4882a593Smuzhiyun 	SOF_FW_BOOT_NOT_STARTED = 0,
346*4882a593Smuzhiyun 	SOF_FW_BOOT_PREPARE,
347*4882a593Smuzhiyun 	SOF_FW_BOOT_IN_PROGRESS,
348*4882a593Smuzhiyun 	SOF_FW_BOOT_FAILED,
349*4882a593Smuzhiyun 	SOF_FW_BOOT_READY_FAILED, /* firmware booted but fw_ready op failed */
350*4882a593Smuzhiyun 	SOF_FW_BOOT_COMPLETE,
351*4882a593Smuzhiyun };
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun /*
354*4882a593Smuzhiyun  * SOF Device Level.
355*4882a593Smuzhiyun  */
356*4882a593Smuzhiyun struct snd_sof_dev {
357*4882a593Smuzhiyun 	struct device *dev;
358*4882a593Smuzhiyun 	spinlock_t ipc_lock;	/* lock for IPC users */
359*4882a593Smuzhiyun 	spinlock_t hw_lock;	/* lock for HW IO access */
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	/*
362*4882a593Smuzhiyun 	 * ASoC components. plat_drv fields are set dynamically so
363*4882a593Smuzhiyun 	 * can't use const
364*4882a593Smuzhiyun 	 */
365*4882a593Smuzhiyun 	struct snd_soc_component_driver plat_drv;
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	/* current DSP power state */
368*4882a593Smuzhiyun 	struct sof_dsp_power_state dsp_power_state;
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	/* Intended power target of system suspend */
371*4882a593Smuzhiyun 	enum sof_system_suspend_state system_suspend_target;
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	/* DSP firmware boot */
374*4882a593Smuzhiyun 	wait_queue_head_t boot_wait;
375*4882a593Smuzhiyun 	enum snd_sof_fw_state fw_state;
376*4882a593Smuzhiyun 	bool first_boot;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	/* work queue in case the probe is implemented in two steps */
379*4882a593Smuzhiyun 	struct work_struct probe_work;
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	/* DSP HW differentiation */
382*4882a593Smuzhiyun 	struct snd_sof_pdata *pdata;
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	/* IPC */
385*4882a593Smuzhiyun 	struct snd_sof_ipc *ipc;
386*4882a593Smuzhiyun 	struct snd_sof_mailbox dsp_box;		/* DSP initiated IPC */
387*4882a593Smuzhiyun 	struct snd_sof_mailbox host_box;	/* Host initiated IPC */
388*4882a593Smuzhiyun 	struct snd_sof_mailbox stream_box;	/* Stream position update */
389*4882a593Smuzhiyun 	struct snd_sof_mailbox debug_box;	/* Debug info updates */
390*4882a593Smuzhiyun 	struct snd_sof_ipc_msg *msg;
391*4882a593Smuzhiyun 	int ipc_irq;
392*4882a593Smuzhiyun 	u32 next_comp_id; /* monotonic - reset during S3 */
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	/* memory bases for mmaped DSPs - set by dsp_init() */
395*4882a593Smuzhiyun 	void __iomem *bar[SND_SOF_BARS];	/* DSP base address */
396*4882a593Smuzhiyun 	int mmio_bar;
397*4882a593Smuzhiyun 	int mailbox_bar;
398*4882a593Smuzhiyun 	size_t dsp_oops_offset;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	/* debug */
401*4882a593Smuzhiyun 	struct dentry *debugfs_root;
402*4882a593Smuzhiyun 	struct list_head dfsentry_list;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	/* firmware loader */
405*4882a593Smuzhiyun 	struct snd_dma_buffer dmab;
406*4882a593Smuzhiyun 	struct snd_dma_buffer dmab_bdl;
407*4882a593Smuzhiyun 	struct sof_ipc_fw_ready fw_ready;
408*4882a593Smuzhiyun 	struct sof_ipc_fw_version fw_version;
409*4882a593Smuzhiyun 	struct sof_ipc_cc_version *cc_version;
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	/* topology */
412*4882a593Smuzhiyun 	struct snd_soc_tplg_ops *tplg_ops;
413*4882a593Smuzhiyun 	struct list_head pcm_list;
414*4882a593Smuzhiyun 	struct list_head kcontrol_list;
415*4882a593Smuzhiyun 	struct list_head widget_list;
416*4882a593Smuzhiyun 	struct list_head dai_list;
417*4882a593Smuzhiyun 	struct list_head route_list;
418*4882a593Smuzhiyun 	struct snd_soc_component *component;
419*4882a593Smuzhiyun 	u32 enabled_cores_mask; /* keep track of enabled cores */
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	/* FW configuration */
422*4882a593Smuzhiyun 	struct sof_ipc_window *info_window;
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	/* IPC timeouts in ms */
425*4882a593Smuzhiyun 	int ipc_timeout;
426*4882a593Smuzhiyun 	int boot_timeout;
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_PROBES)
429*4882a593Smuzhiyun 	unsigned int extractor_stream_tag;
430*4882a593Smuzhiyun #endif
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	/* DMA for Trace */
433*4882a593Smuzhiyun 	struct snd_dma_buffer dmatb;
434*4882a593Smuzhiyun 	struct snd_dma_buffer dmatp;
435*4882a593Smuzhiyun 	int dma_trace_pages;
436*4882a593Smuzhiyun 	wait_queue_head_t trace_sleep;
437*4882a593Smuzhiyun 	u32 host_offset;
438*4882a593Smuzhiyun 	bool dtrace_is_supported; /* set with Kconfig or module parameter */
439*4882a593Smuzhiyun 	bool dtrace_is_enabled;
440*4882a593Smuzhiyun 	bool dtrace_error;
441*4882a593Smuzhiyun 	bool dtrace_draining;
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	bool msi_enabled;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	void *private;			/* core does not touch this */
446*4882a593Smuzhiyun };
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun /*
449*4882a593Smuzhiyun  * Device Level.
450*4882a593Smuzhiyun  */
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun int snd_sof_device_probe(struct device *dev, struct snd_sof_pdata *plat_data);
453*4882a593Smuzhiyun int snd_sof_device_remove(struct device *dev);
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun int snd_sof_runtime_suspend(struct device *dev);
456*4882a593Smuzhiyun int snd_sof_runtime_resume(struct device *dev);
457*4882a593Smuzhiyun int snd_sof_runtime_idle(struct device *dev);
458*4882a593Smuzhiyun int snd_sof_resume(struct device *dev);
459*4882a593Smuzhiyun int snd_sof_suspend(struct device *dev);
460*4882a593Smuzhiyun int snd_sof_dsp_power_down_notify(struct snd_sof_dev *sdev);
461*4882a593Smuzhiyun int snd_sof_prepare(struct device *dev);
462*4882a593Smuzhiyun void snd_sof_complete(struct device *dev);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun void snd_sof_new_platform_drv(struct snd_sof_dev *sdev);
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun int snd_sof_create_page_table(struct device *dev,
467*4882a593Smuzhiyun 			      struct snd_dma_buffer *dmab,
468*4882a593Smuzhiyun 			      unsigned char *page_table, size_t size);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun /*
471*4882a593Smuzhiyun  * Firmware loading.
472*4882a593Smuzhiyun  */
473*4882a593Smuzhiyun int snd_sof_load_firmware(struct snd_sof_dev *sdev);
474*4882a593Smuzhiyun int snd_sof_load_firmware_raw(struct snd_sof_dev *sdev);
475*4882a593Smuzhiyun int snd_sof_load_firmware_memcpy(struct snd_sof_dev *sdev);
476*4882a593Smuzhiyun int snd_sof_run_firmware(struct snd_sof_dev *sdev);
477*4882a593Smuzhiyun int snd_sof_parse_module_memcpy(struct snd_sof_dev *sdev,
478*4882a593Smuzhiyun 				struct snd_sof_mod_hdr *module);
479*4882a593Smuzhiyun void snd_sof_fw_unload(struct snd_sof_dev *sdev);
480*4882a593Smuzhiyun int snd_sof_fw_parse_ext_data(struct snd_sof_dev *sdev, u32 bar, u32 offset);
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun /*
483*4882a593Smuzhiyun  * IPC low level APIs.
484*4882a593Smuzhiyun  */
485*4882a593Smuzhiyun struct snd_sof_ipc *snd_sof_ipc_init(struct snd_sof_dev *sdev);
486*4882a593Smuzhiyun void snd_sof_ipc_free(struct snd_sof_dev *sdev);
487*4882a593Smuzhiyun void snd_sof_ipc_reply(struct snd_sof_dev *sdev, u32 msg_id);
488*4882a593Smuzhiyun void snd_sof_ipc_msgs_rx(struct snd_sof_dev *sdev);
489*4882a593Smuzhiyun int snd_sof_ipc_stream_pcm_params(struct snd_sof_dev *sdev,
490*4882a593Smuzhiyun 				  struct sof_ipc_pcm_params *params);
491*4882a593Smuzhiyun int snd_sof_dsp_mailbox_init(struct snd_sof_dev *sdev, u32 dspbox,
492*4882a593Smuzhiyun 			     size_t dspbox_size, u32 hostbox,
493*4882a593Smuzhiyun 			     size_t hostbox_size);
494*4882a593Smuzhiyun int snd_sof_ipc_valid(struct snd_sof_dev *sdev);
495*4882a593Smuzhiyun int sof_ipc_tx_message(struct snd_sof_ipc *ipc, u32 header,
496*4882a593Smuzhiyun 		       void *msg_data, size_t msg_bytes, void *reply_data,
497*4882a593Smuzhiyun 		       size_t reply_bytes);
498*4882a593Smuzhiyun int sof_ipc_tx_message_no_pm(struct snd_sof_ipc *ipc, u32 header,
499*4882a593Smuzhiyun 			     void *msg_data, size_t msg_bytes,
500*4882a593Smuzhiyun 			     void *reply_data, size_t reply_bytes);
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun /*
503*4882a593Smuzhiyun  * Trace/debug
504*4882a593Smuzhiyun  */
505*4882a593Smuzhiyun int snd_sof_init_trace(struct snd_sof_dev *sdev);
506*4882a593Smuzhiyun void snd_sof_release_trace(struct snd_sof_dev *sdev);
507*4882a593Smuzhiyun void snd_sof_free_trace(struct snd_sof_dev *sdev);
508*4882a593Smuzhiyun int snd_sof_dbg_init(struct snd_sof_dev *sdev);
509*4882a593Smuzhiyun void snd_sof_free_debug(struct snd_sof_dev *sdev);
510*4882a593Smuzhiyun int snd_sof_debugfs_io_item(struct snd_sof_dev *sdev,
511*4882a593Smuzhiyun 			    void __iomem *base, size_t size,
512*4882a593Smuzhiyun 			    const char *name,
513*4882a593Smuzhiyun 			    enum sof_debugfs_access_type access_type);
514*4882a593Smuzhiyun int snd_sof_debugfs_buf_item(struct snd_sof_dev *sdev,
515*4882a593Smuzhiyun 			     void *base, size_t size,
516*4882a593Smuzhiyun 			     const char *name, mode_t mode);
517*4882a593Smuzhiyun int snd_sof_trace_update_pos(struct snd_sof_dev *sdev,
518*4882a593Smuzhiyun 			     struct sof_ipc_dma_trace_posn *posn);
519*4882a593Smuzhiyun void snd_sof_trace_notify_for_error(struct snd_sof_dev *sdev);
520*4882a593Smuzhiyun void snd_sof_get_status(struct snd_sof_dev *sdev, u32 panic_code,
521*4882a593Smuzhiyun 			u32 tracep_code, void *oops,
522*4882a593Smuzhiyun 			struct sof_ipc_panic_info *panic_info,
523*4882a593Smuzhiyun 			void *stack, size_t stack_words);
524*4882a593Smuzhiyun int snd_sof_init_trace_ipc(struct snd_sof_dev *sdev);
525*4882a593Smuzhiyun void snd_sof_handle_fw_exception(struct snd_sof_dev *sdev);
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun /*
528*4882a593Smuzhiyun  * Platform specific ops.
529*4882a593Smuzhiyun  */
530*4882a593Smuzhiyun extern struct snd_compress_ops sof_compressed_ops;
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun /*
533*4882a593Smuzhiyun  * DSP Architectures.
534*4882a593Smuzhiyun  */
sof_stack(struct snd_sof_dev * sdev,void * oops,u32 * stack,u32 stack_words)535*4882a593Smuzhiyun static inline void sof_stack(struct snd_sof_dev *sdev, void *oops, u32 *stack,
536*4882a593Smuzhiyun 			     u32 stack_words)
537*4882a593Smuzhiyun {
538*4882a593Smuzhiyun 		sof_arch_ops(sdev)->dsp_stack(sdev, oops, stack, stack_words);
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun 
sof_oops(struct snd_sof_dev * sdev,void * oops)541*4882a593Smuzhiyun static inline void sof_oops(struct snd_sof_dev *sdev, void *oops)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun 	if (sof_arch_ops(sdev)->dsp_oops)
544*4882a593Smuzhiyun 		sof_arch_ops(sdev)->dsp_oops(sdev, oops);
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun extern const struct sof_arch_ops sof_xtensa_arch_ops;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun /*
550*4882a593Smuzhiyun  * Utilities
551*4882a593Smuzhiyun  */
552*4882a593Smuzhiyun void sof_io_write(struct snd_sof_dev *sdev, void __iomem *addr, u32 value);
553*4882a593Smuzhiyun void sof_io_write64(struct snd_sof_dev *sdev, void __iomem *addr, u64 value);
554*4882a593Smuzhiyun u32 sof_io_read(struct snd_sof_dev *sdev, void __iomem *addr);
555*4882a593Smuzhiyun u64 sof_io_read64(struct snd_sof_dev *sdev, void __iomem *addr);
556*4882a593Smuzhiyun void sof_mailbox_write(struct snd_sof_dev *sdev, u32 offset,
557*4882a593Smuzhiyun 		       void *message, size_t bytes);
558*4882a593Smuzhiyun void sof_mailbox_read(struct snd_sof_dev *sdev, u32 offset,
559*4882a593Smuzhiyun 		      void *message, size_t bytes);
560*4882a593Smuzhiyun void sof_block_write(struct snd_sof_dev *sdev, u32 bar, u32 offset, void *src,
561*4882a593Smuzhiyun 		     size_t size);
562*4882a593Smuzhiyun void sof_block_read(struct snd_sof_dev *sdev, u32 bar, u32 offset, void *dest,
563*4882a593Smuzhiyun 		    size_t size);
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun int sof_fw_ready(struct snd_sof_dev *sdev, u32 msg_id);
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun void intel_ipc_msg_data(struct snd_sof_dev *sdev,
568*4882a593Smuzhiyun 			struct snd_pcm_substream *substream,
569*4882a593Smuzhiyun 			void *p, size_t sz);
570*4882a593Smuzhiyun int intel_ipc_pcm_params(struct snd_sof_dev *sdev,
571*4882a593Smuzhiyun 			 struct snd_pcm_substream *substream,
572*4882a593Smuzhiyun 			 const struct sof_ipc_pcm_params_reply *reply);
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun int intel_pcm_open(struct snd_sof_dev *sdev,
575*4882a593Smuzhiyun 		   struct snd_pcm_substream *substream);
576*4882a593Smuzhiyun int intel_pcm_close(struct snd_sof_dev *sdev,
577*4882a593Smuzhiyun 		    struct snd_pcm_substream *substream);
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun int sof_machine_check(struct snd_sof_dev *sdev);
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun #define sof_dev_dbg_or_err(dev, is_err, fmt, ...)			\
582*4882a593Smuzhiyun 	do {								\
583*4882a593Smuzhiyun 		if (is_err)						\
584*4882a593Smuzhiyun 			dev_err(dev, "error: " fmt, __VA_ARGS__);	\
585*4882a593Smuzhiyun 		else							\
586*4882a593Smuzhiyun 			dev_dbg(dev, fmt, __VA_ARGS__);			\
587*4882a593Smuzhiyun 	} while (0)
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun #endif
590