1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // This file is provided under a dual BSD/GPLv2 license. When using or
4*4882a593Smuzhiyun // redistributing this file, you may do so under either license.
5*4882a593Smuzhiyun //
6*4882a593Smuzhiyun // Copyright(c) 2018 Intel Corporation. All rights reserved.
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9*4882a593Smuzhiyun // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10*4882a593Smuzhiyun // Rander Wang <rander.wang@intel.com>
11*4882a593Smuzhiyun // Keyon Jie <yang.jie@linux.intel.com>
12*4882a593Smuzhiyun //
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /*
15*4882a593Smuzhiyun * Hardware interface for generic Intel audio DSP HDA IP
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <sound/hdaudio_ext.h>
19*4882a593Smuzhiyun #include <sound/hda_register.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/acpi.h>
22*4882a593Smuzhiyun #include <linux/module.h>
23*4882a593Smuzhiyun #include <linux/soundwire/sdw.h>
24*4882a593Smuzhiyun #include <linux/soundwire/sdw_intel.h>
25*4882a593Smuzhiyun #include <sound/intel-nhlt.h>
26*4882a593Smuzhiyun #include <sound/sof.h>
27*4882a593Smuzhiyun #include <sound/sof/xtensa.h>
28*4882a593Smuzhiyun #include "../sof-audio.h"
29*4882a593Smuzhiyun #include "../ops.h"
30*4882a593Smuzhiyun #include "hda.h"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
33*4882a593Smuzhiyun #include <sound/soc-acpi-intel-match.h>
34*4882a593Smuzhiyun #endif
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* platform specific devices */
37*4882a593Smuzhiyun #include "shim.h"
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define EXCEPT_MAX_HDR_SIZE 0x400
40*4882a593Smuzhiyun #define HDA_EXT_ROM_STATUS_SIZE 8
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static const struct sof_intel_dsp_desc
get_chip_info(struct snd_sof_pdata * pdata)43*4882a593Smuzhiyun *get_chip_info(struct snd_sof_pdata *pdata)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun const struct sof_dev_desc *desc = pdata->desc;
46*4882a593Smuzhiyun const struct sof_intel_dsp_desc *chip_info;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun chip_info = desc->chip_info;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun return chip_info;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * The default for SoundWire clock stop quirks is to power gate the IP
57*4882a593Smuzhiyun * and do a Bus Reset, this will need to be modified when the DSP
58*4882a593Smuzhiyun * needs to remain in D0i3 so that the Master does not lose context
59*4882a593Smuzhiyun * and enumeration is not required on clock restart
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET;
62*4882a593Smuzhiyun module_param(sdw_clock_stop_quirks, int, 0444);
63*4882a593Smuzhiyun MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks");
64*4882a593Smuzhiyun
sdw_params_stream(struct device * dev,struct sdw_intel_stream_params_data * params_data)65*4882a593Smuzhiyun static int sdw_params_stream(struct device *dev,
66*4882a593Smuzhiyun struct sdw_intel_stream_params_data *params_data)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct snd_sof_dev *sdev = dev_get_drvdata(dev);
69*4882a593Smuzhiyun struct snd_soc_dai *d = params_data->dai;
70*4882a593Smuzhiyun struct sof_ipc_dai_config config;
71*4882a593Smuzhiyun struct sof_ipc_reply reply;
72*4882a593Smuzhiyun int link_id = params_data->link_id;
73*4882a593Smuzhiyun int alh_stream_id = params_data->alh_stream_id;
74*4882a593Smuzhiyun int ret;
75*4882a593Smuzhiyun u32 size = sizeof(config);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun memset(&config, 0, size);
78*4882a593Smuzhiyun config.hdr.size = size;
79*4882a593Smuzhiyun config.hdr.cmd = SOF_IPC_GLB_DAI_MSG | SOF_IPC_DAI_CONFIG;
80*4882a593Smuzhiyun config.type = SOF_DAI_INTEL_ALH;
81*4882a593Smuzhiyun config.dai_index = (link_id << 8) | (d->id);
82*4882a593Smuzhiyun config.alh.stream_id = alh_stream_id;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* send message to DSP */
85*4882a593Smuzhiyun ret = sof_ipc_tx_message(sdev->ipc,
86*4882a593Smuzhiyun config.hdr.cmd, &config, size, &reply,
87*4882a593Smuzhiyun sizeof(reply));
88*4882a593Smuzhiyun if (ret < 0) {
89*4882a593Smuzhiyun dev_err(sdev->dev,
90*4882a593Smuzhiyun "error: failed to set DAI hw_params for link %d dai->id %d ALH %d\n",
91*4882a593Smuzhiyun link_id, d->id, alh_stream_id);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun return ret;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
sdw_free_stream(struct device * dev,struct sdw_intel_stream_free_data * free_data)97*4882a593Smuzhiyun static int sdw_free_stream(struct device *dev,
98*4882a593Smuzhiyun struct sdw_intel_stream_free_data *free_data)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun struct snd_sof_dev *sdev = dev_get_drvdata(dev);
101*4882a593Smuzhiyun struct snd_soc_dai *d = free_data->dai;
102*4882a593Smuzhiyun struct sof_ipc_dai_config config;
103*4882a593Smuzhiyun struct sof_ipc_reply reply;
104*4882a593Smuzhiyun int link_id = free_data->link_id;
105*4882a593Smuzhiyun int ret;
106*4882a593Smuzhiyun u32 size = sizeof(config);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun memset(&config, 0, size);
109*4882a593Smuzhiyun config.hdr.size = size;
110*4882a593Smuzhiyun config.hdr.cmd = SOF_IPC_GLB_DAI_MSG | SOF_IPC_DAI_CONFIG;
111*4882a593Smuzhiyun config.type = SOF_DAI_INTEL_ALH;
112*4882a593Smuzhiyun config.dai_index = (link_id << 8) | d->id;
113*4882a593Smuzhiyun config.alh.stream_id = 0xFFFF; /* invalid value on purpose */
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* send message to DSP */
116*4882a593Smuzhiyun ret = sof_ipc_tx_message(sdev->ipc,
117*4882a593Smuzhiyun config.hdr.cmd, &config, size, &reply,
118*4882a593Smuzhiyun sizeof(reply));
119*4882a593Smuzhiyun if (ret < 0) {
120*4882a593Smuzhiyun dev_err(sdev->dev,
121*4882a593Smuzhiyun "error: failed to free stream for link %d dai->id %d\n",
122*4882a593Smuzhiyun link_id, d->id);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return ret;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static const struct sdw_intel_ops sdw_callback = {
129*4882a593Smuzhiyun .params_stream = sdw_params_stream,
130*4882a593Smuzhiyun .free_stream = sdw_free_stream,
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
hda_sdw_int_enable(struct snd_sof_dev * sdev,bool enable)133*4882a593Smuzhiyun void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun sdw_intel_enable_irq(sdev->bar[HDA_DSP_BAR], enable);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
hda_sdw_acpi_scan(struct snd_sof_dev * sdev)138*4882a593Smuzhiyun static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev;
141*4882a593Smuzhiyun acpi_handle handle;
142*4882a593Smuzhiyun int ret;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun handle = ACPI_HANDLE(sdev->dev);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /* save ACPI info for the probe step */
147*4882a593Smuzhiyun hdev = sdev->pdata->hw_pdata;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun ret = sdw_intel_acpi_scan(handle, &hdev->info);
150*4882a593Smuzhiyun if (ret < 0)
151*4882a593Smuzhiyun return -EINVAL;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun return 0;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
hda_sdw_probe(struct snd_sof_dev * sdev)156*4882a593Smuzhiyun static int hda_sdw_probe(struct snd_sof_dev *sdev)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev;
159*4882a593Smuzhiyun struct sdw_intel_res res;
160*4882a593Smuzhiyun void *sdw;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun hdev = sdev->pdata->hw_pdata;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun memset(&res, 0, sizeof(res));
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun res.mmio_base = sdev->bar[HDA_DSP_BAR];
167*4882a593Smuzhiyun res.irq = sdev->ipc_irq;
168*4882a593Smuzhiyun res.handle = hdev->info.handle;
169*4882a593Smuzhiyun res.parent = sdev->dev;
170*4882a593Smuzhiyun res.ops = &sdw_callback;
171*4882a593Smuzhiyun res.dev = sdev->dev;
172*4882a593Smuzhiyun res.clock_stop_quirks = sdw_clock_stop_quirks;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /*
175*4882a593Smuzhiyun * ops and arg fields are not populated for now,
176*4882a593Smuzhiyun * they will be needed when the DAI callbacks are
177*4882a593Smuzhiyun * provided
178*4882a593Smuzhiyun */
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun /* we could filter links here if needed, e.g for quirks */
181*4882a593Smuzhiyun res.count = hdev->info.count;
182*4882a593Smuzhiyun res.link_mask = hdev->info.link_mask;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun sdw = sdw_intel_probe(&res);
185*4882a593Smuzhiyun if (!sdw) {
186*4882a593Smuzhiyun dev_err(sdev->dev, "error: SoundWire probe failed\n");
187*4882a593Smuzhiyun return -EINVAL;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* save context */
191*4882a593Smuzhiyun hdev->sdw = sdw;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun return 0;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
hda_sdw_startup(struct snd_sof_dev * sdev)196*4882a593Smuzhiyun int hda_sdw_startup(struct snd_sof_dev *sdev)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun hdev = sdev->pdata->hw_pdata;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun if (!hdev->sdw)
203*4882a593Smuzhiyun return 0;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun return sdw_intel_startup(hdev->sdw);
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
hda_sdw_exit(struct snd_sof_dev * sdev)208*4882a593Smuzhiyun static int hda_sdw_exit(struct snd_sof_dev *sdev)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun hdev = sdev->pdata->hw_pdata;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun hda_sdw_int_enable(sdev, false);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun if (hdev->sdw)
217*4882a593Smuzhiyun sdw_intel_exit(hdev->sdw);
218*4882a593Smuzhiyun hdev->sdw = NULL;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun return 0;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
hda_dsp_check_sdw_irq(struct snd_sof_dev * sdev)223*4882a593Smuzhiyun static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev;
226*4882a593Smuzhiyun bool ret = false;
227*4882a593Smuzhiyun u32 irq_status;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun hdev = sdev->pdata->hw_pdata;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun if (!hdev->sdw)
232*4882a593Smuzhiyun return ret;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* store status */
235*4882a593Smuzhiyun irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /* invalid message ? */
238*4882a593Smuzhiyun if (irq_status == 0xffffffff)
239*4882a593Smuzhiyun goto out;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /* SDW message ? */
242*4882a593Smuzhiyun if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW)
243*4882a593Smuzhiyun ret = true;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun out:
246*4882a593Smuzhiyun return ret;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
hda_dsp_sdw_thread(int irq,void * context)249*4882a593Smuzhiyun static irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun return sdw_intel_thread(irq, context);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
hda_sdw_check_wakeen_irq(struct snd_sof_dev * sdev)254*4882a593Smuzhiyun static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun hdev = sdev->pdata->hw_pdata;
259*4882a593Smuzhiyun if (hdev->sdw &&
260*4882a593Smuzhiyun snd_sof_dsp_read(sdev, HDA_DSP_BAR,
261*4882a593Smuzhiyun HDA_DSP_REG_SNDW_WAKE_STS))
262*4882a593Smuzhiyun return true;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun return false;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
hda_sdw_process_wakeen(struct snd_sof_dev * sdev)267*4882a593Smuzhiyun void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun hdev = sdev->pdata->hw_pdata;
272*4882a593Smuzhiyun if (!hdev->sdw)
273*4882a593Smuzhiyun return;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun sdw_intel_process_wakeen_event(hdev->sdw);
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun #endif
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun /*
281*4882a593Smuzhiyun * Debug
282*4882a593Smuzhiyun */
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun struct hda_dsp_msg_code {
285*4882a593Smuzhiyun u32 code;
286*4882a593Smuzhiyun const char *msg;
287*4882a593Smuzhiyun };
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun static bool hda_use_msi = IS_ENABLED(CONFIG_PCI);
290*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
291*4882a593Smuzhiyun module_param_named(use_msi, hda_use_msi, bool, 0444);
292*4882a593Smuzhiyun MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode");
293*4882a593Smuzhiyun #endif
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun static char *hda_model;
296*4882a593Smuzhiyun module_param(hda_model, charp, 0444);
297*4882a593Smuzhiyun MODULE_PARM_DESC(hda_model, "Use the given HDA board model.");
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
300*4882a593Smuzhiyun static int hda_dmic_num = -1;
301*4882a593Smuzhiyun module_param_named(dmic_num, hda_dmic_num, int, 0444);
302*4882a593Smuzhiyun MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number");
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun static bool hda_codec_use_common_hdmi = IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI);
305*4882a593Smuzhiyun module_param_named(use_common_hdmi, hda_codec_use_common_hdmi, bool, 0444);
306*4882a593Smuzhiyun MODULE_PARM_DESC(use_common_hdmi, "SOF HDA use common HDMI codec driver");
307*4882a593Smuzhiyun #endif
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
310*4882a593Smuzhiyun {HDA_DSP_ROM_FW_MANIFEST_LOADED, "status: manifest loaded"},
311*4882a593Smuzhiyun {HDA_DSP_ROM_FW_FW_LOADED, "status: fw loaded"},
312*4882a593Smuzhiyun {HDA_DSP_ROM_FW_ENTERED, "status: fw entered"},
313*4882a593Smuzhiyun {HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
314*4882a593Smuzhiyun {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
315*4882a593Smuzhiyun {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
316*4882a593Smuzhiyun {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
317*4882a593Smuzhiyun {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
318*4882a593Smuzhiyun {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
319*4882a593Smuzhiyun {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
320*4882a593Smuzhiyun {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
321*4882a593Smuzhiyun {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
322*4882a593Smuzhiyun {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
323*4882a593Smuzhiyun {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
324*4882a593Smuzhiyun {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
325*4882a593Smuzhiyun {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
326*4882a593Smuzhiyun {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
327*4882a593Smuzhiyun {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
328*4882a593Smuzhiyun {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
329*4882a593Smuzhiyun };
330*4882a593Smuzhiyun
hda_dsp_get_status_skl(struct snd_sof_dev * sdev)331*4882a593Smuzhiyun static void hda_dsp_get_status_skl(struct snd_sof_dev *sdev)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun u32 status;
334*4882a593Smuzhiyun int i;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
337*4882a593Smuzhiyun HDA_ADSP_FW_STATUS_SKL);
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
340*4882a593Smuzhiyun if (status == hda_dsp_rom_msg[i].code) {
341*4882a593Smuzhiyun dev_err(sdev->dev, "%s - code %8.8x\n",
342*4882a593Smuzhiyun hda_dsp_rom_msg[i].msg, status);
343*4882a593Smuzhiyun return;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun /* not for us, must be generic sof message */
348*4882a593Smuzhiyun dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
hda_dsp_get_status(struct snd_sof_dev * sdev)351*4882a593Smuzhiyun static void hda_dsp_get_status(struct snd_sof_dev *sdev)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun u32 status;
354*4882a593Smuzhiyun int i;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
357*4882a593Smuzhiyun HDA_DSP_SRAM_REG_ROM_STATUS);
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
360*4882a593Smuzhiyun if (status == hda_dsp_rom_msg[i].code) {
361*4882a593Smuzhiyun dev_err(sdev->dev, "%s - code %8.8x\n",
362*4882a593Smuzhiyun hda_dsp_rom_msg[i].msg, status);
363*4882a593Smuzhiyun return;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /* not for us, must be generic sof message */
368*4882a593Smuzhiyun dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
hda_dsp_get_registers(struct snd_sof_dev * sdev,struct sof_ipc_dsp_oops_xtensa * xoops,struct sof_ipc_panic_info * panic_info,u32 * stack,size_t stack_words)371*4882a593Smuzhiyun static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
372*4882a593Smuzhiyun struct sof_ipc_dsp_oops_xtensa *xoops,
373*4882a593Smuzhiyun struct sof_ipc_panic_info *panic_info,
374*4882a593Smuzhiyun u32 *stack, size_t stack_words)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun u32 offset = sdev->dsp_oops_offset;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* first read registers */
379*4882a593Smuzhiyun sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun /* note: variable AR register array is not read */
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun /* then get panic info */
384*4882a593Smuzhiyun if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
385*4882a593Smuzhiyun dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
386*4882a593Smuzhiyun xoops->arch_hdr.totalsize);
387*4882a593Smuzhiyun return;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun offset += xoops->arch_hdr.totalsize;
390*4882a593Smuzhiyun sof_block_read(sdev, sdev->mmio_bar, offset,
391*4882a593Smuzhiyun panic_info, sizeof(*panic_info));
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun /* then get the stack */
394*4882a593Smuzhiyun offset += sizeof(*panic_info);
395*4882a593Smuzhiyun sof_block_read(sdev, sdev->mmio_bar, offset, stack,
396*4882a593Smuzhiyun stack_words * sizeof(u32));
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
hda_dsp_dump_skl(struct snd_sof_dev * sdev,u32 flags)399*4882a593Smuzhiyun void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun struct sof_ipc_dsp_oops_xtensa xoops;
402*4882a593Smuzhiyun struct sof_ipc_panic_info panic_info;
403*4882a593Smuzhiyun u32 stack[HDA_DSP_STACK_DUMP_SIZE];
404*4882a593Smuzhiyun u32 status, panic;
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun /* try APL specific status message types first */
407*4882a593Smuzhiyun hda_dsp_get_status_skl(sdev);
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun /* now try generic SOF status messages */
410*4882a593Smuzhiyun status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
411*4882a593Smuzhiyun HDA_ADSP_ERROR_CODE_SKL);
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun /*TODO: Check: there is no define in spec, but it is used in the code*/
414*4882a593Smuzhiyun panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
415*4882a593Smuzhiyun HDA_ADSP_ERROR_CODE_SKL + 0x4);
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun if (sdev->fw_state == SOF_FW_BOOT_COMPLETE) {
418*4882a593Smuzhiyun hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
419*4882a593Smuzhiyun HDA_DSP_STACK_DUMP_SIZE);
420*4882a593Smuzhiyun snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
421*4882a593Smuzhiyun stack, HDA_DSP_STACK_DUMP_SIZE);
422*4882a593Smuzhiyun } else {
423*4882a593Smuzhiyun dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
424*4882a593Smuzhiyun status, panic);
425*4882a593Smuzhiyun hda_dsp_get_status_skl(sdev);
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun /* dump the first 8 dwords representing the extended ROM status */
hda_dsp_dump_ext_rom_status(struct snd_sof_dev * sdev)430*4882a593Smuzhiyun static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev)
431*4882a593Smuzhiyun {
432*4882a593Smuzhiyun struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
433*4882a593Smuzhiyun char msg[128];
434*4882a593Smuzhiyun int len = 0;
435*4882a593Smuzhiyun u32 value;
436*4882a593Smuzhiyun int i;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) {
439*4882a593Smuzhiyun value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_ROM_STATUS + i * 0x4);
440*4882a593Smuzhiyun len += snprintf(msg + len, sizeof(msg) - len, " 0x%x", value);
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun sof_dev_dbg_or_err(sdev->dev, hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS,
444*4882a593Smuzhiyun "extended rom status: %s", msg);
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
hda_dsp_dump(struct snd_sof_dev * sdev,u32 flags)448*4882a593Smuzhiyun void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
449*4882a593Smuzhiyun {
450*4882a593Smuzhiyun struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
451*4882a593Smuzhiyun struct sof_ipc_dsp_oops_xtensa xoops;
452*4882a593Smuzhiyun struct sof_ipc_panic_info panic_info;
453*4882a593Smuzhiyun u32 stack[HDA_DSP_STACK_DUMP_SIZE];
454*4882a593Smuzhiyun u32 status, panic;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun /* try APL specific status message types first */
457*4882a593Smuzhiyun hda_dsp_get_status(sdev);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun /* now try generic SOF status messages */
460*4882a593Smuzhiyun status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
461*4882a593Smuzhiyun HDA_DSP_SRAM_REG_FW_STATUS);
462*4882a593Smuzhiyun panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun if (sdev->fw_state == SOF_FW_BOOT_COMPLETE) {
465*4882a593Smuzhiyun hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
466*4882a593Smuzhiyun HDA_DSP_STACK_DUMP_SIZE);
467*4882a593Smuzhiyun snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
468*4882a593Smuzhiyun stack, HDA_DSP_STACK_DUMP_SIZE);
469*4882a593Smuzhiyun } else {
470*4882a593Smuzhiyun sof_dev_dbg_or_err(sdev->dev, hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS,
471*4882a593Smuzhiyun "status = 0x%8.8x panic = 0x%8.8x\n",
472*4882a593Smuzhiyun status, panic);
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun hda_dsp_dump_ext_rom_status(sdev);
475*4882a593Smuzhiyun hda_dsp_get_status(sdev);
476*4882a593Smuzhiyun }
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun
hda_ipc_irq_dump(struct snd_sof_dev * sdev)479*4882a593Smuzhiyun void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
480*4882a593Smuzhiyun {
481*4882a593Smuzhiyun struct hdac_bus *bus = sof_to_bus(sdev);
482*4882a593Smuzhiyun u32 adspis;
483*4882a593Smuzhiyun u32 intsts;
484*4882a593Smuzhiyun u32 intctl;
485*4882a593Smuzhiyun u32 ppsts;
486*4882a593Smuzhiyun u8 rirbsts;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun /* read key IRQ stats and config registers */
489*4882a593Smuzhiyun adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
490*4882a593Smuzhiyun intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
491*4882a593Smuzhiyun intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
492*4882a593Smuzhiyun ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
493*4882a593Smuzhiyun rirbsts = snd_hdac_chip_readb(bus, RIRBSTS);
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun dev_err(sdev->dev,
496*4882a593Smuzhiyun "error: hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
497*4882a593Smuzhiyun intsts, intctl, rirbsts);
498*4882a593Smuzhiyun dev_err(sdev->dev,
499*4882a593Smuzhiyun "error: dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n",
500*4882a593Smuzhiyun ppsts, adspis);
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun
hda_ipc_dump(struct snd_sof_dev * sdev)503*4882a593Smuzhiyun void hda_ipc_dump(struct snd_sof_dev *sdev)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun u32 hipcie;
506*4882a593Smuzhiyun u32 hipct;
507*4882a593Smuzhiyun u32 hipcctl;
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun hda_ipc_irq_dump(sdev);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun /* read IPC status */
512*4882a593Smuzhiyun hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
513*4882a593Smuzhiyun hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
514*4882a593Smuzhiyun hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun /* dump the IPC regs */
517*4882a593Smuzhiyun /* TODO: parse the raw msg */
518*4882a593Smuzhiyun dev_err(sdev->dev,
519*4882a593Smuzhiyun "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
520*4882a593Smuzhiyun hipcie, hipct, hipcctl);
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
hda_init(struct snd_sof_dev * sdev)523*4882a593Smuzhiyun static int hda_init(struct snd_sof_dev *sdev)
524*4882a593Smuzhiyun {
525*4882a593Smuzhiyun struct hda_bus *hbus;
526*4882a593Smuzhiyun struct hdac_bus *bus;
527*4882a593Smuzhiyun struct pci_dev *pci = to_pci_dev(sdev->dev);
528*4882a593Smuzhiyun int ret;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun hbus = sof_to_hbus(sdev);
531*4882a593Smuzhiyun bus = sof_to_bus(sdev);
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun /* HDA bus init */
534*4882a593Smuzhiyun sof_hda_bus_init(bus, &pci->dev);
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun bus->use_posbuf = 1;
537*4882a593Smuzhiyun bus->bdl_pos_adj = 0;
538*4882a593Smuzhiyun bus->sync_write = 1;
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun mutex_init(&hbus->prepare_mutex);
541*4882a593Smuzhiyun hbus->pci = pci;
542*4882a593Smuzhiyun hbus->mixer_assigned = -1;
543*4882a593Smuzhiyun hbus->modelname = hda_model;
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun /* initialise hdac bus */
546*4882a593Smuzhiyun bus->addr = pci_resource_start(pci, 0);
547*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_PCI)
548*4882a593Smuzhiyun bus->remap_addr = pci_ioremap_bar(pci, 0);
549*4882a593Smuzhiyun #endif
550*4882a593Smuzhiyun if (!bus->remap_addr) {
551*4882a593Smuzhiyun dev_err(bus->dev, "error: ioremap error\n");
552*4882a593Smuzhiyun return -ENXIO;
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun /* HDA base */
556*4882a593Smuzhiyun sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun /* init i915 and HDMI codecs */
559*4882a593Smuzhiyun ret = hda_codec_i915_init(sdev);
560*4882a593Smuzhiyun if (ret < 0)
561*4882a593Smuzhiyun dev_warn(sdev->dev, "init of i915 and HDMI codec failed\n");
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun /* get controller capabilities */
564*4882a593Smuzhiyun ret = hda_dsp_ctrl_get_caps(sdev);
565*4882a593Smuzhiyun if (ret < 0)
566*4882a593Smuzhiyun dev_err(sdev->dev, "error: get caps error\n");
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun return ret;
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
572*4882a593Smuzhiyun
check_nhlt_dmic(struct snd_sof_dev * sdev)573*4882a593Smuzhiyun static int check_nhlt_dmic(struct snd_sof_dev *sdev)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun struct nhlt_acpi_table *nhlt;
576*4882a593Smuzhiyun int dmic_num;
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun nhlt = intel_nhlt_init(sdev->dev);
579*4882a593Smuzhiyun if (nhlt) {
580*4882a593Smuzhiyun dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt);
581*4882a593Smuzhiyun intel_nhlt_free(nhlt);
582*4882a593Smuzhiyun if (dmic_num >= 1 && dmic_num <= 4)
583*4882a593Smuzhiyun return dmic_num;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun return 0;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun
fixup_tplg_name(struct snd_sof_dev * sdev,const char * sof_tplg_filename,const char * idisp_str,const char * dmic_str)589*4882a593Smuzhiyun static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
590*4882a593Smuzhiyun const char *sof_tplg_filename,
591*4882a593Smuzhiyun const char *idisp_str,
592*4882a593Smuzhiyun const char *dmic_str)
593*4882a593Smuzhiyun {
594*4882a593Smuzhiyun const char *tplg_filename = NULL;
595*4882a593Smuzhiyun char *filename;
596*4882a593Smuzhiyun char *split_ext;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
599*4882a593Smuzhiyun if (!filename)
600*4882a593Smuzhiyun return NULL;
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun /* this assumes a .tplg extension */
603*4882a593Smuzhiyun split_ext = strsep(&filename, ".");
604*4882a593Smuzhiyun if (split_ext) {
605*4882a593Smuzhiyun tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
606*4882a593Smuzhiyun "%s%s%s.tplg",
607*4882a593Smuzhiyun split_ext, idisp_str, dmic_str);
608*4882a593Smuzhiyun if (!tplg_filename)
609*4882a593Smuzhiyun return NULL;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun return tplg_filename;
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun #endif
615*4882a593Smuzhiyun
hda_init_caps(struct snd_sof_dev * sdev)616*4882a593Smuzhiyun static int hda_init_caps(struct snd_sof_dev *sdev)
617*4882a593Smuzhiyun {
618*4882a593Smuzhiyun struct hdac_bus *bus = sof_to_bus(sdev);
619*4882a593Smuzhiyun struct snd_sof_pdata *pdata = sdev->pdata;
620*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
621*4882a593Smuzhiyun struct hdac_ext_link *hlink;
622*4882a593Smuzhiyun #endif
623*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev = pdata->hw_pdata;
624*4882a593Smuzhiyun u32 link_mask;
625*4882a593Smuzhiyun int ret = 0;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun device_disable_async_suspend(bus->dev);
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun /* check if dsp is there */
630*4882a593Smuzhiyun if (bus->ppcap)
631*4882a593Smuzhiyun dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun /* Init HDA controller after i915 init */
634*4882a593Smuzhiyun ret = hda_dsp_ctrl_init_chip(sdev, true);
635*4882a593Smuzhiyun if (ret < 0) {
636*4882a593Smuzhiyun dev_err(bus->dev, "error: init chip failed with ret: %d\n",
637*4882a593Smuzhiyun ret);
638*4882a593Smuzhiyun return ret;
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun /* scan SoundWire capabilities exposed by DSDT */
642*4882a593Smuzhiyun ret = hda_sdw_acpi_scan(sdev);
643*4882a593Smuzhiyun if (ret < 0) {
644*4882a593Smuzhiyun dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n");
645*4882a593Smuzhiyun goto skip_soundwire;
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun link_mask = hdev->info.link_mask;
649*4882a593Smuzhiyun if (!link_mask) {
650*4882a593Smuzhiyun dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n");
651*4882a593Smuzhiyun goto skip_soundwire;
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun /*
655*4882a593Smuzhiyun * probe/allocate SoundWire resources.
656*4882a593Smuzhiyun * The hardware configuration takes place in hda_sdw_startup
657*4882a593Smuzhiyun * after power rails are enabled.
658*4882a593Smuzhiyun * It's entirely possible to have a mix of I2S/DMIC/SoundWire
659*4882a593Smuzhiyun * devices, so we allocate the resources in all cases.
660*4882a593Smuzhiyun */
661*4882a593Smuzhiyun ret = hda_sdw_probe(sdev);
662*4882a593Smuzhiyun if (ret < 0) {
663*4882a593Smuzhiyun dev_err(sdev->dev, "error: SoundWire probe error\n");
664*4882a593Smuzhiyun return ret;
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun skip_soundwire:
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
670*4882a593Smuzhiyun if (bus->mlcap)
671*4882a593Smuzhiyun snd_hdac_ext_bus_get_ml_capabilities(bus);
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun /* create codec instances */
674*4882a593Smuzhiyun hda_codec_probe_bus(sdev, hda_codec_use_common_hdmi);
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun if (!HDA_IDISP_CODEC(bus->codec_mask))
677*4882a593Smuzhiyun hda_codec_i915_display_power(sdev, false);
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun /*
680*4882a593Smuzhiyun * we are done probing so decrement link counts
681*4882a593Smuzhiyun */
682*4882a593Smuzhiyun list_for_each_entry(hlink, &bus->hlink_list, list)
683*4882a593Smuzhiyun snd_hdac_ext_bus_link_put(bus, hlink);
684*4882a593Smuzhiyun #endif
685*4882a593Smuzhiyun return 0;
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun
hda_dsp_interrupt_handler(int irq,void * context)688*4882a593Smuzhiyun static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context)
689*4882a593Smuzhiyun {
690*4882a593Smuzhiyun struct snd_sof_dev *sdev = context;
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun /*
693*4882a593Smuzhiyun * Get global interrupt status. It includes all hardware interrupt
694*4882a593Smuzhiyun * sources in the Intel HD Audio controller.
695*4882a593Smuzhiyun */
696*4882a593Smuzhiyun if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) &
697*4882a593Smuzhiyun SOF_HDA_INTSTS_GIS) {
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun /* disable GIE interrupt */
700*4882a593Smuzhiyun snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
701*4882a593Smuzhiyun SOF_HDA_INTCTL,
702*4882a593Smuzhiyun SOF_HDA_INT_GLOBAL_EN,
703*4882a593Smuzhiyun 0);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun return IRQ_WAKE_THREAD;
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun return IRQ_NONE;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun
hda_dsp_interrupt_thread(int irq,void * context)711*4882a593Smuzhiyun static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context)
712*4882a593Smuzhiyun {
713*4882a593Smuzhiyun struct snd_sof_dev *sdev = context;
714*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun /* deal with streams and controller first */
717*4882a593Smuzhiyun if (hda_dsp_check_stream_irq(sdev))
718*4882a593Smuzhiyun hda_dsp_stream_threaded_handler(irq, sdev);
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun if (hda_dsp_check_ipc_irq(sdev))
721*4882a593Smuzhiyun sof_ops(sdev)->irq_thread(irq, sdev);
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun if (hda_dsp_check_sdw_irq(sdev))
724*4882a593Smuzhiyun hda_dsp_sdw_thread(irq, hdev->sdw);
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun if (hda_sdw_check_wakeen_irq(sdev))
727*4882a593Smuzhiyun hda_sdw_process_wakeen(sdev);
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun /* enable GIE interrupt */
730*4882a593Smuzhiyun snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
731*4882a593Smuzhiyun SOF_HDA_INTCTL,
732*4882a593Smuzhiyun SOF_HDA_INT_GLOBAL_EN,
733*4882a593Smuzhiyun SOF_HDA_INT_GLOBAL_EN);
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun return IRQ_HANDLED;
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun
hda_dsp_probe(struct snd_sof_dev * sdev)738*4882a593Smuzhiyun int hda_dsp_probe(struct snd_sof_dev *sdev)
739*4882a593Smuzhiyun {
740*4882a593Smuzhiyun struct pci_dev *pci = to_pci_dev(sdev->dev);
741*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev;
742*4882a593Smuzhiyun struct hdac_bus *bus;
743*4882a593Smuzhiyun const struct sof_intel_dsp_desc *chip;
744*4882a593Smuzhiyun int ret = 0;
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun /*
747*4882a593Smuzhiyun * detect DSP by checking class/subclass/prog-id information
748*4882a593Smuzhiyun * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required
749*4882a593Smuzhiyun * class=04 subclass 01 prog-if 00: DSP is present
750*4882a593Smuzhiyun * (and may be required e.g. for DMIC or SSP support)
751*4882a593Smuzhiyun * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works
752*4882a593Smuzhiyun */
753*4882a593Smuzhiyun if (pci->class == 0x040300) {
754*4882a593Smuzhiyun dev_err(sdev->dev, "error: the DSP is not enabled on this platform, aborting probe\n");
755*4882a593Smuzhiyun return -ENODEV;
756*4882a593Smuzhiyun } else if (pci->class != 0x040100 && pci->class != 0x040380) {
757*4882a593Smuzhiyun dev_err(sdev->dev, "error: unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", pci->class);
758*4882a593Smuzhiyun return -ENODEV;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", pci->class);
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun chip = get_chip_info(sdev->pdata);
763*4882a593Smuzhiyun if (!chip) {
764*4882a593Smuzhiyun dev_err(sdev->dev, "error: no such device supported, chip id:%x\n",
765*4882a593Smuzhiyun pci->device);
766*4882a593Smuzhiyun ret = -EIO;
767*4882a593Smuzhiyun goto err;
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL);
771*4882a593Smuzhiyun if (!hdev)
772*4882a593Smuzhiyun return -ENOMEM;
773*4882a593Smuzhiyun sdev->pdata->hw_pdata = hdev;
774*4882a593Smuzhiyun hdev->desc = chip;
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
777*4882a593Smuzhiyun PLATFORM_DEVID_NONE,
778*4882a593Smuzhiyun NULL, 0);
779*4882a593Smuzhiyun if (IS_ERR(hdev->dmic_dev)) {
780*4882a593Smuzhiyun dev_err(sdev->dev, "error: failed to create DMIC device\n");
781*4882a593Smuzhiyun return PTR_ERR(hdev->dmic_dev);
782*4882a593Smuzhiyun }
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun /*
785*4882a593Smuzhiyun * use position update IPC if either it is forced
786*4882a593Smuzhiyun * or we don't have other choice
787*4882a593Smuzhiyun */
788*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
789*4882a593Smuzhiyun hdev->no_ipc_position = 0;
790*4882a593Smuzhiyun #else
791*4882a593Smuzhiyun hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0;
792*4882a593Smuzhiyun #endif
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun /* set up HDA base */
795*4882a593Smuzhiyun bus = sof_to_bus(sdev);
796*4882a593Smuzhiyun ret = hda_init(sdev);
797*4882a593Smuzhiyun if (ret < 0)
798*4882a593Smuzhiyun goto hdac_bus_unmap;
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun /* DSP base */
801*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_PCI)
802*4882a593Smuzhiyun sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
803*4882a593Smuzhiyun #endif
804*4882a593Smuzhiyun if (!sdev->bar[HDA_DSP_BAR]) {
805*4882a593Smuzhiyun dev_err(sdev->dev, "error: ioremap error\n");
806*4882a593Smuzhiyun ret = -ENXIO;
807*4882a593Smuzhiyun goto hdac_bus_unmap;
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun sdev->mmio_bar = HDA_DSP_BAR;
811*4882a593Smuzhiyun sdev->mailbox_bar = HDA_DSP_BAR;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun /* allow 64bit DMA address if supported by H/W */
814*4882a593Smuzhiyun if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(64))) {
815*4882a593Smuzhiyun dev_dbg(sdev->dev, "DMA mask is 64 bit\n");
816*4882a593Smuzhiyun dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(64));
817*4882a593Smuzhiyun } else {
818*4882a593Smuzhiyun dev_dbg(sdev->dev, "DMA mask is 32 bit\n");
819*4882a593Smuzhiyun dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
820*4882a593Smuzhiyun dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun /* init streams */
824*4882a593Smuzhiyun ret = hda_dsp_stream_init(sdev);
825*4882a593Smuzhiyun if (ret < 0) {
826*4882a593Smuzhiyun dev_err(sdev->dev, "error: failed to init streams\n");
827*4882a593Smuzhiyun /*
828*4882a593Smuzhiyun * not all errors are due to memory issues, but trying
829*4882a593Smuzhiyun * to free everything does not harm
830*4882a593Smuzhiyun */
831*4882a593Smuzhiyun goto free_streams;
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun /*
835*4882a593Smuzhiyun * register our IRQ
836*4882a593Smuzhiyun * let's try to enable msi firstly
837*4882a593Smuzhiyun * if it fails, use legacy interrupt mode
838*4882a593Smuzhiyun * TODO: support msi multiple vectors
839*4882a593Smuzhiyun */
840*4882a593Smuzhiyun if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) {
841*4882a593Smuzhiyun dev_info(sdev->dev, "use msi interrupt mode\n");
842*4882a593Smuzhiyun sdev->ipc_irq = pci_irq_vector(pci, 0);
843*4882a593Smuzhiyun /* initialised to "false" by kzalloc() */
844*4882a593Smuzhiyun sdev->msi_enabled = true;
845*4882a593Smuzhiyun }
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun if (!sdev->msi_enabled) {
848*4882a593Smuzhiyun dev_info(sdev->dev, "use legacy interrupt mode\n");
849*4882a593Smuzhiyun /*
850*4882a593Smuzhiyun * in IO-APIC mode, hda->irq and ipc_irq are using the same
851*4882a593Smuzhiyun * irq number of pci->irq
852*4882a593Smuzhiyun */
853*4882a593Smuzhiyun sdev->ipc_irq = pci->irq;
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
857*4882a593Smuzhiyun ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler,
858*4882a593Smuzhiyun hda_dsp_interrupt_thread,
859*4882a593Smuzhiyun IRQF_SHARED, "AudioDSP", sdev);
860*4882a593Smuzhiyun if (ret < 0) {
861*4882a593Smuzhiyun dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
862*4882a593Smuzhiyun sdev->ipc_irq);
863*4882a593Smuzhiyun goto free_irq_vector;
864*4882a593Smuzhiyun }
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun pci_set_master(pci);
867*4882a593Smuzhiyun synchronize_irq(pci->irq);
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun /*
870*4882a593Smuzhiyun * clear TCSEL to clear playback on some HD Audio
871*4882a593Smuzhiyun * codecs. PCI TCSEL is defined in the Intel manuals.
872*4882a593Smuzhiyun */
873*4882a593Smuzhiyun snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun /* init HDA capabilities */
876*4882a593Smuzhiyun ret = hda_init_caps(sdev);
877*4882a593Smuzhiyun if (ret < 0)
878*4882a593Smuzhiyun goto free_ipc_irq;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun /* enable ppcap interrupt */
881*4882a593Smuzhiyun hda_dsp_ctrl_ppcap_enable(sdev, true);
882*4882a593Smuzhiyun hda_dsp_ctrl_ppcap_int_enable(sdev, true);
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun /* set default mailbox offset for FW ready message */
885*4882a593Smuzhiyun sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work);
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun return 0;
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun free_ipc_irq:
892*4882a593Smuzhiyun free_irq(sdev->ipc_irq, sdev);
893*4882a593Smuzhiyun free_irq_vector:
894*4882a593Smuzhiyun if (sdev->msi_enabled)
895*4882a593Smuzhiyun pci_free_irq_vectors(pci);
896*4882a593Smuzhiyun free_streams:
897*4882a593Smuzhiyun hda_dsp_stream_free(sdev);
898*4882a593Smuzhiyun /* dsp_unmap: not currently used */
899*4882a593Smuzhiyun iounmap(sdev->bar[HDA_DSP_BAR]);
900*4882a593Smuzhiyun hdac_bus_unmap:
901*4882a593Smuzhiyun platform_device_unregister(hdev->dmic_dev);
902*4882a593Smuzhiyun iounmap(bus->remap_addr);
903*4882a593Smuzhiyun hda_codec_i915_exit(sdev);
904*4882a593Smuzhiyun err:
905*4882a593Smuzhiyun return ret;
906*4882a593Smuzhiyun }
907*4882a593Smuzhiyun
hda_dsp_remove(struct snd_sof_dev * sdev)908*4882a593Smuzhiyun int hda_dsp_remove(struct snd_sof_dev *sdev)
909*4882a593Smuzhiyun {
910*4882a593Smuzhiyun struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
911*4882a593Smuzhiyun struct hdac_bus *bus = sof_to_bus(sdev);
912*4882a593Smuzhiyun struct pci_dev *pci = to_pci_dev(sdev->dev);
913*4882a593Smuzhiyun const struct sof_intel_dsp_desc *chip = hda->desc;
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun /* cancel any attempt for DSP D0I3 */
916*4882a593Smuzhiyun cancel_delayed_work_sync(&hda->d0i3_work);
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
919*4882a593Smuzhiyun /* codec removal, invoke bus_device_remove */
920*4882a593Smuzhiyun snd_hdac_ext_bus_device_remove(bus);
921*4882a593Smuzhiyun #endif
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun hda_sdw_exit(sdev);
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(hda->dmic_dev))
926*4882a593Smuzhiyun platform_device_unregister(hda->dmic_dev);
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun /* disable DSP IRQ */
929*4882a593Smuzhiyun snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
930*4882a593Smuzhiyun SOF_HDA_PPCTL_PIE, 0);
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun /* disable CIE and GIE interrupts */
933*4882a593Smuzhiyun snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
934*4882a593Smuzhiyun SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0);
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun /* disable cores */
937*4882a593Smuzhiyun if (chip)
938*4882a593Smuzhiyun hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun /* disable DSP */
941*4882a593Smuzhiyun snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
942*4882a593Smuzhiyun SOF_HDA_PPCTL_GPROCEN, 0);
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun free_irq(sdev->ipc_irq, sdev);
945*4882a593Smuzhiyun if (sdev->msi_enabled)
946*4882a593Smuzhiyun pci_free_irq_vectors(pci);
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun hda_dsp_stream_free(sdev);
949*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
950*4882a593Smuzhiyun snd_hdac_link_free_all(bus);
951*4882a593Smuzhiyun #endif
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun iounmap(sdev->bar[HDA_DSP_BAR]);
954*4882a593Smuzhiyun iounmap(bus->remap_addr);
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
957*4882a593Smuzhiyun snd_hdac_ext_bus_exit(bus);
958*4882a593Smuzhiyun #endif
959*4882a593Smuzhiyun hda_codec_i915_exit(sdev);
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun return 0;
962*4882a593Smuzhiyun }
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
hda_generic_machine_select(struct snd_sof_dev * sdev)965*4882a593Smuzhiyun static int hda_generic_machine_select(struct snd_sof_dev *sdev)
966*4882a593Smuzhiyun {
967*4882a593Smuzhiyun struct hdac_bus *bus = sof_to_bus(sdev);
968*4882a593Smuzhiyun struct snd_soc_acpi_mach_params *mach_params;
969*4882a593Smuzhiyun struct snd_soc_acpi_mach *hda_mach;
970*4882a593Smuzhiyun struct snd_sof_pdata *pdata = sdev->pdata;
971*4882a593Smuzhiyun const char *tplg_filename;
972*4882a593Smuzhiyun const char *idisp_str;
973*4882a593Smuzhiyun const char *dmic_str;
974*4882a593Smuzhiyun int dmic_num = 0;
975*4882a593Smuzhiyun int codec_num = 0;
976*4882a593Smuzhiyun int i;
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun /* codec detection */
979*4882a593Smuzhiyun if (!bus->codec_mask) {
980*4882a593Smuzhiyun dev_info(bus->dev, "no hda codecs found!\n");
981*4882a593Smuzhiyun } else {
982*4882a593Smuzhiyun dev_info(bus->dev, "hda codecs found, mask %lx\n",
983*4882a593Smuzhiyun bus->codec_mask);
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun for (i = 0; i < HDA_MAX_CODECS; i++) {
986*4882a593Smuzhiyun if (bus->codec_mask & (1 << i))
987*4882a593Smuzhiyun codec_num++;
988*4882a593Smuzhiyun }
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun /*
991*4882a593Smuzhiyun * If no machine driver is found, then:
992*4882a593Smuzhiyun *
993*4882a593Smuzhiyun * generic hda machine driver can handle:
994*4882a593Smuzhiyun * - one HDMI codec, and/or
995*4882a593Smuzhiyun * - one external HDAudio codec
996*4882a593Smuzhiyun */
997*4882a593Smuzhiyun if (!pdata->machine && codec_num <= 2) {
998*4882a593Smuzhiyun hda_mach = snd_soc_acpi_intel_hda_machines;
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun /* topology: use the info from hda_machines */
1001*4882a593Smuzhiyun pdata->tplg_filename =
1002*4882a593Smuzhiyun hda_mach->sof_tplg_filename;
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun dev_info(bus->dev, "using HDA machine driver %s now\n",
1005*4882a593Smuzhiyun hda_mach->drv_name);
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask))
1008*4882a593Smuzhiyun idisp_str = "-idisp";
1009*4882a593Smuzhiyun else
1010*4882a593Smuzhiyun idisp_str = "";
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun /* first check NHLT for DMICs */
1013*4882a593Smuzhiyun dmic_num = check_nhlt_dmic(sdev);
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun /* allow for module parameter override */
1016*4882a593Smuzhiyun if (hda_dmic_num != -1)
1017*4882a593Smuzhiyun dmic_num = hda_dmic_num;
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun switch (dmic_num) {
1020*4882a593Smuzhiyun case 1:
1021*4882a593Smuzhiyun dmic_str = "-1ch";
1022*4882a593Smuzhiyun break;
1023*4882a593Smuzhiyun case 2:
1024*4882a593Smuzhiyun dmic_str = "-2ch";
1025*4882a593Smuzhiyun break;
1026*4882a593Smuzhiyun case 3:
1027*4882a593Smuzhiyun dmic_str = "-3ch";
1028*4882a593Smuzhiyun break;
1029*4882a593Smuzhiyun case 4:
1030*4882a593Smuzhiyun dmic_str = "-4ch";
1031*4882a593Smuzhiyun break;
1032*4882a593Smuzhiyun default:
1033*4882a593Smuzhiyun dmic_num = 0;
1034*4882a593Smuzhiyun dmic_str = "";
1035*4882a593Smuzhiyun break;
1036*4882a593Smuzhiyun }
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun tplg_filename = pdata->tplg_filename;
1039*4882a593Smuzhiyun tplg_filename = fixup_tplg_name(sdev, tplg_filename,
1040*4882a593Smuzhiyun idisp_str, dmic_str);
1041*4882a593Smuzhiyun if (!tplg_filename)
1042*4882a593Smuzhiyun return -EINVAL;
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun dev_info(bus->dev,
1045*4882a593Smuzhiyun "DMICs detected in NHLT tables: %d\n",
1046*4882a593Smuzhiyun dmic_num);
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun pdata->machine = hda_mach;
1049*4882a593Smuzhiyun pdata->tplg_filename = tplg_filename;
1050*4882a593Smuzhiyun }
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun /* used by hda machine driver to create dai links */
1054*4882a593Smuzhiyun if (pdata->machine) {
1055*4882a593Smuzhiyun mach_params = (struct snd_soc_acpi_mach_params *)
1056*4882a593Smuzhiyun &pdata->machine->mach_params;
1057*4882a593Smuzhiyun mach_params->codec_mask = bus->codec_mask;
1058*4882a593Smuzhiyun mach_params->common_hdmi_codec_drv = hda_codec_use_common_hdmi;
1059*4882a593Smuzhiyun mach_params->dmic_num = dmic_num;
1060*4882a593Smuzhiyun }
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun return 0;
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun #else
hda_generic_machine_select(struct snd_sof_dev * sdev)1065*4882a593Smuzhiyun static int hda_generic_machine_select(struct snd_sof_dev *sdev)
1066*4882a593Smuzhiyun {
1067*4882a593Smuzhiyun return 0;
1068*4882a593Smuzhiyun }
1069*4882a593Smuzhiyun #endif
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
1072*4882a593Smuzhiyun /* Check if all Slaves defined on the link can be found */
link_slaves_found(struct snd_sof_dev * sdev,const struct snd_soc_acpi_link_adr * link,struct sdw_intel_ctx * sdw)1073*4882a593Smuzhiyun static bool link_slaves_found(struct snd_sof_dev *sdev,
1074*4882a593Smuzhiyun const struct snd_soc_acpi_link_adr *link,
1075*4882a593Smuzhiyun struct sdw_intel_ctx *sdw)
1076*4882a593Smuzhiyun {
1077*4882a593Smuzhiyun struct hdac_bus *bus = sof_to_bus(sdev);
1078*4882a593Smuzhiyun struct sdw_intel_slave_id *ids = sdw->ids;
1079*4882a593Smuzhiyun int num_slaves = sdw->num_slaves;
1080*4882a593Smuzhiyun unsigned int part_id, link_id, unique_id, mfg_id;
1081*4882a593Smuzhiyun int i, j;
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun for (i = 0; i < link->num_adr; i++) {
1084*4882a593Smuzhiyun u64 adr = link->adr_d[i].adr;
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun mfg_id = SDW_MFG_ID(adr);
1087*4882a593Smuzhiyun part_id = SDW_PART_ID(adr);
1088*4882a593Smuzhiyun link_id = SDW_DISCO_LINK_ID(adr);
1089*4882a593Smuzhiyun for (j = 0; j < num_slaves; j++) {
1090*4882a593Smuzhiyun if (ids[j].link_id != link_id ||
1091*4882a593Smuzhiyun ids[j].id.part_id != part_id ||
1092*4882a593Smuzhiyun ids[j].id.mfg_id != mfg_id)
1093*4882a593Smuzhiyun continue;
1094*4882a593Smuzhiyun /*
1095*4882a593Smuzhiyun * we have to check unique id
1096*4882a593Smuzhiyun * if there is more than one
1097*4882a593Smuzhiyun * Slave on the link
1098*4882a593Smuzhiyun */
1099*4882a593Smuzhiyun unique_id = SDW_UNIQUE_ID(adr);
1100*4882a593Smuzhiyun if (link->num_adr == 1 ||
1101*4882a593Smuzhiyun ids[j].id.unique_id == SDW_IGNORED_UNIQUE_ID ||
1102*4882a593Smuzhiyun ids[j].id.unique_id == unique_id) {
1103*4882a593Smuzhiyun dev_dbg(bus->dev,
1104*4882a593Smuzhiyun "found %x at link %d\n",
1105*4882a593Smuzhiyun part_id, link_id);
1106*4882a593Smuzhiyun break;
1107*4882a593Smuzhiyun }
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun if (j == num_slaves) {
1110*4882a593Smuzhiyun dev_dbg(bus->dev,
1111*4882a593Smuzhiyun "Slave %x not found\n",
1112*4882a593Smuzhiyun part_id);
1113*4882a593Smuzhiyun return false;
1114*4882a593Smuzhiyun }
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun return true;
1117*4882a593Smuzhiyun }
1118*4882a593Smuzhiyun
hda_sdw_machine_select(struct snd_sof_dev * sdev)1119*4882a593Smuzhiyun static int hda_sdw_machine_select(struct snd_sof_dev *sdev)
1120*4882a593Smuzhiyun {
1121*4882a593Smuzhiyun struct snd_sof_pdata *pdata = sdev->pdata;
1122*4882a593Smuzhiyun const struct snd_soc_acpi_link_adr *link;
1123*4882a593Smuzhiyun struct hdac_bus *bus = sof_to_bus(sdev);
1124*4882a593Smuzhiyun struct snd_soc_acpi_mach *mach;
1125*4882a593Smuzhiyun struct sof_intel_hda_dev *hdev;
1126*4882a593Smuzhiyun u32 link_mask;
1127*4882a593Smuzhiyun int i;
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun hdev = pdata->hw_pdata;
1130*4882a593Smuzhiyun link_mask = hdev->info.link_mask;
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun /*
1133*4882a593Smuzhiyun * Select SoundWire machine driver if needed using the
1134*4882a593Smuzhiyun * alternate tables. This case deals with SoundWire-only
1135*4882a593Smuzhiyun * machines, for mixed cases with I2C/I2S the detection relies
1136*4882a593Smuzhiyun * on the HID list.
1137*4882a593Smuzhiyun */
1138*4882a593Smuzhiyun if (link_mask && !pdata->machine) {
1139*4882a593Smuzhiyun for (mach = pdata->desc->alt_machines;
1140*4882a593Smuzhiyun mach && mach->link_mask; mach++) {
1141*4882a593Smuzhiyun /*
1142*4882a593Smuzhiyun * On some platforms such as Up Extreme all links
1143*4882a593Smuzhiyun * are enabled but only one link can be used by
1144*4882a593Smuzhiyun * external codec. Instead of exact match of two masks,
1145*4882a593Smuzhiyun * first check whether link_mask of mach is subset of
1146*4882a593Smuzhiyun * link_mask supported by hw and then go on searching
1147*4882a593Smuzhiyun * link_adr
1148*4882a593Smuzhiyun */
1149*4882a593Smuzhiyun if (~link_mask & mach->link_mask)
1150*4882a593Smuzhiyun continue;
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun /* No need to match adr if there is no links defined */
1153*4882a593Smuzhiyun if (!mach->links)
1154*4882a593Smuzhiyun break;
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun link = mach->links;
1157*4882a593Smuzhiyun for (i = 0; i < hdev->info.count && link->num_adr;
1158*4882a593Smuzhiyun i++, link++) {
1159*4882a593Smuzhiyun /*
1160*4882a593Smuzhiyun * Try next machine if any expected Slaves
1161*4882a593Smuzhiyun * are not found on this link.
1162*4882a593Smuzhiyun */
1163*4882a593Smuzhiyun if (!link_slaves_found(sdev, link, hdev->sdw))
1164*4882a593Smuzhiyun break;
1165*4882a593Smuzhiyun }
1166*4882a593Smuzhiyun /* Found if all Slaves are checked */
1167*4882a593Smuzhiyun if (i == hdev->info.count || !link->num_adr)
1168*4882a593Smuzhiyun break;
1169*4882a593Smuzhiyun }
1170*4882a593Smuzhiyun if (mach && mach->link_mask) {
1171*4882a593Smuzhiyun dev_dbg(bus->dev,
1172*4882a593Smuzhiyun "SoundWire machine driver %s topology %s\n",
1173*4882a593Smuzhiyun mach->drv_name,
1174*4882a593Smuzhiyun mach->sof_tplg_filename);
1175*4882a593Smuzhiyun pdata->machine = mach;
1176*4882a593Smuzhiyun mach->mach_params.links = mach->links;
1177*4882a593Smuzhiyun mach->mach_params.link_mask = mach->link_mask;
1178*4882a593Smuzhiyun mach->mach_params.platform = dev_name(sdev->dev);
1179*4882a593Smuzhiyun pdata->fw_filename = mach->sof_fw_filename;
1180*4882a593Smuzhiyun pdata->tplg_filename = mach->sof_tplg_filename;
1181*4882a593Smuzhiyun } else {
1182*4882a593Smuzhiyun dev_info(sdev->dev,
1183*4882a593Smuzhiyun "No SoundWire machine driver found\n");
1184*4882a593Smuzhiyun }
1185*4882a593Smuzhiyun }
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun return 0;
1188*4882a593Smuzhiyun }
1189*4882a593Smuzhiyun #else
hda_sdw_machine_select(struct snd_sof_dev * sdev)1190*4882a593Smuzhiyun static int hda_sdw_machine_select(struct snd_sof_dev *sdev)
1191*4882a593Smuzhiyun {
1192*4882a593Smuzhiyun return 0;
1193*4882a593Smuzhiyun }
1194*4882a593Smuzhiyun #endif
1195*4882a593Smuzhiyun
hda_set_mach_params(const struct snd_soc_acpi_mach * mach,struct device * dev)1196*4882a593Smuzhiyun void hda_set_mach_params(const struct snd_soc_acpi_mach *mach,
1197*4882a593Smuzhiyun struct device *dev)
1198*4882a593Smuzhiyun {
1199*4882a593Smuzhiyun struct snd_soc_acpi_mach_params *mach_params;
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params;
1202*4882a593Smuzhiyun mach_params->platform = dev_name(dev);
1203*4882a593Smuzhiyun }
1204*4882a593Smuzhiyun
hda_machine_select(struct snd_sof_dev * sdev)1205*4882a593Smuzhiyun void hda_machine_select(struct snd_sof_dev *sdev)
1206*4882a593Smuzhiyun {
1207*4882a593Smuzhiyun struct snd_sof_pdata *sof_pdata = sdev->pdata;
1208*4882a593Smuzhiyun const struct sof_dev_desc *desc = sof_pdata->desc;
1209*4882a593Smuzhiyun struct snd_soc_acpi_mach *mach;
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun mach = snd_soc_acpi_find_machine(desc->machines);
1212*4882a593Smuzhiyun if (mach) {
1213*4882a593Smuzhiyun /*
1214*4882a593Smuzhiyun * If tplg file name is overridden, use it instead of
1215*4882a593Smuzhiyun * the one set in mach table
1216*4882a593Smuzhiyun */
1217*4882a593Smuzhiyun if (!sof_pdata->tplg_filename)
1218*4882a593Smuzhiyun sof_pdata->tplg_filename = mach->sof_tplg_filename;
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun sof_pdata->machine = mach;
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun if (mach->link_mask) {
1223*4882a593Smuzhiyun mach->mach_params.links = mach->links;
1224*4882a593Smuzhiyun mach->mach_params.link_mask = mach->link_mask;
1225*4882a593Smuzhiyun }
1226*4882a593Smuzhiyun }
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun /*
1229*4882a593Smuzhiyun * If I2S fails, try SoundWire
1230*4882a593Smuzhiyun */
1231*4882a593Smuzhiyun hda_sdw_machine_select(sdev);
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun /*
1234*4882a593Smuzhiyun * Choose HDA generic machine driver if mach is NULL.
1235*4882a593Smuzhiyun * Otherwise, set certain mach params.
1236*4882a593Smuzhiyun */
1237*4882a593Smuzhiyun hda_generic_machine_select(sdev);
1238*4882a593Smuzhiyun
1239*4882a593Smuzhiyun if (!sof_pdata->machine)
1240*4882a593Smuzhiyun dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
1241*4882a593Smuzhiyun }
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
1244*4882a593Smuzhiyun MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC);
1245*4882a593Smuzhiyun MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915);
1246*4882a593Smuzhiyun MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
1247*4882a593Smuzhiyun MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT);
1248