1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or 4*4882a593Smuzhiyun * redistributing this file, you may do so under either license. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright(c) 2019 Intel Corporation. All rights reserved. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Keyon Jie <yang.jie@linux.intel.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __SOF_INTEL_HDA_IPC_H 12*4882a593Smuzhiyun #define __SOF_INTEL_HDA_IPC_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Primary register, mapped to 16*4882a593Smuzhiyun * - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+) 17*4882a593Smuzhiyun * - DIPCT in cAVS 1.5 IPC 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * Secondary register, mapped to: 20*4882a593Smuzhiyun * - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+) 21*4882a593Smuzhiyun * - DIPCTE in cAVS 1.5 IPC 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Common bits in primary register */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Reserved for doorbell */ 27*4882a593Smuzhiyun #define HDA_IPC_RSVD_31 BIT(31) 28*4882a593Smuzhiyun /* Target, 0 - normal message, 1 - compact message(cAVS compatible) */ 29*4882a593Smuzhiyun #define HDA_IPC_MSG_COMPACT BIT(30) 30*4882a593Smuzhiyun /* Direction, 0 - request, 1 - response */ 31*4882a593Smuzhiyun #define HDA_IPC_RSP BIT(29) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define HDA_IPC_TYPE_SHIFT 24 34*4882a593Smuzhiyun #define HDA_IPC_TYPE_MASK GENMASK(28, 24) 35*4882a593Smuzhiyun #define HDA_IPC_TYPE(x) ((x) << HDA_IPC_TYPE_SHIFT) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define HDA_IPC_PM_GATE HDA_IPC_TYPE(0x8U) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Command specific payload bits in secondary register */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Disable DMA tracing (0 - keep tracing, 1 - to disable DMA trace) */ 42*4882a593Smuzhiyun #define HDA_PM_NO_DMA_TRACE BIT(4) 43*4882a593Smuzhiyun /* Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */ 44*4882a593Smuzhiyun #define HDA_PM_PCG BIT(3) 45*4882a593Smuzhiyun /* Prevent power gating (0 - deep power state transitions allowed) */ 46*4882a593Smuzhiyun #define HDA_PM_PPG BIT(2) 47*4882a593Smuzhiyun /* Indicates whether streaming is active */ 48*4882a593Smuzhiyun #define HDA_PM_PG_STREAMING BIT(1) 49*4882a593Smuzhiyun #define HDA_PM_PG_RSVD BIT(0) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun irqreturn_t cnl_ipc_irq_thread(int irq, void *context); 52*4882a593Smuzhiyun int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 53*4882a593Smuzhiyun void cnl_ipc_dump(struct snd_sof_dev *sdev); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif 56