1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // SH7760 ("camelot") DMABRG audio DMA unit support
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun // The SH7760 DMABRG provides 4 dma channels (2x rec, 2x play), which
8*4882a593Smuzhiyun // trigger an interrupt when one half of the programmed transfer size
9*4882a593Smuzhiyun // has been xmitted.
10*4882a593Smuzhiyun //
11*4882a593Smuzhiyun // FIXME: little-endian only for now
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/gfp.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/dma-mapping.h>
18*4882a593Smuzhiyun #include <sound/core.h>
19*4882a593Smuzhiyun #include <sound/pcm.h>
20*4882a593Smuzhiyun #include <sound/pcm_params.h>
21*4882a593Smuzhiyun #include <sound/soc.h>
22*4882a593Smuzhiyun #include <asm/dmabrg.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* registers and bits */
26*4882a593Smuzhiyun #define BRGATXSAR 0x00
27*4882a593Smuzhiyun #define BRGARXDAR 0x04
28*4882a593Smuzhiyun #define BRGATXTCR 0x08
29*4882a593Smuzhiyun #define BRGARXTCR 0x0C
30*4882a593Smuzhiyun #define BRGACR 0x10
31*4882a593Smuzhiyun #define BRGATXTCNT 0x14
32*4882a593Smuzhiyun #define BRGARXTCNT 0x18
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define ACR_RAR (1 << 18)
35*4882a593Smuzhiyun #define ACR_RDS (1 << 17)
36*4882a593Smuzhiyun #define ACR_RDE (1 << 16)
37*4882a593Smuzhiyun #define ACR_TAR (1 << 2)
38*4882a593Smuzhiyun #define ACR_TDS (1 << 1)
39*4882a593Smuzhiyun #define ACR_TDE (1 << 0)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* receiver/transmitter data alignment */
42*4882a593Smuzhiyun #define ACR_RAM_NONE (0 << 24)
43*4882a593Smuzhiyun #define ACR_RAM_4BYTE (1 << 24)
44*4882a593Smuzhiyun #define ACR_RAM_2WORD (2 << 24)
45*4882a593Smuzhiyun #define ACR_TAM_NONE (0 << 8)
46*4882a593Smuzhiyun #define ACR_TAM_4BYTE (1 << 8)
47*4882a593Smuzhiyun #define ACR_TAM_2WORD (2 << 8)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun struct camelot_pcm {
51*4882a593Smuzhiyun unsigned long mmio; /* DMABRG audio channel control reg MMIO */
52*4882a593Smuzhiyun unsigned int txid; /* ID of first DMABRG IRQ for this unit */
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun struct snd_pcm_substream *tx_ss;
55*4882a593Smuzhiyun unsigned long tx_period_size;
56*4882a593Smuzhiyun unsigned int tx_period;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun struct snd_pcm_substream *rx_ss;
59*4882a593Smuzhiyun unsigned long rx_period_size;
60*4882a593Smuzhiyun unsigned int rx_period;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun } cam_pcm_data[2] = {
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun .mmio = 0xFE3C0040,
65*4882a593Smuzhiyun .txid = DMABRGIRQ_A0TXF,
66*4882a593Smuzhiyun },
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun .mmio = 0xFE3C0060,
69*4882a593Smuzhiyun .txid = DMABRGIRQ_A1TXF,
70*4882a593Smuzhiyun },
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #define BRGREG(x) (*(unsigned long *)(cam->mmio + (x)))
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun * set a minimum of 16kb per period, to avoid interrupt-"storm" and
77*4882a593Smuzhiyun * resulting skipping. In general, the bigger the minimum size, the
78*4882a593Smuzhiyun * better for overall system performance. (The SH7760 is a puny CPU
79*4882a593Smuzhiyun * with a slow SDRAM interface and poor internal bus bandwidth,
80*4882a593Smuzhiyun * *especially* when the LCDC is active). The minimum for the DMAC
81*4882a593Smuzhiyun * is 8 bytes; 16kbytes are enough to get skip-free playback of a
82*4882a593Smuzhiyun * 44kHz/16bit/stereo MP3 on a lightly loaded system, and maintain
83*4882a593Smuzhiyun * reasonable responsiveness in MPlayer.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun #define DMABRG_PERIOD_MIN 16 * 1024
86*4882a593Smuzhiyun #define DMABRG_PERIOD_MAX 0x03fffffc
87*4882a593Smuzhiyun #define DMABRG_PREALLOC_BUFFER 32 * 1024
88*4882a593Smuzhiyun #define DMABRG_PREALLOC_BUFFER_MAX 32 * 1024
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun static const struct snd_pcm_hardware camelot_pcm_hardware = {
91*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP |
92*4882a593Smuzhiyun SNDRV_PCM_INFO_INTERLEAVED |
93*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
94*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
95*4882a593Smuzhiyun SNDRV_PCM_INFO_BATCH),
96*4882a593Smuzhiyun .buffer_bytes_max = DMABRG_PERIOD_MAX,
97*4882a593Smuzhiyun .period_bytes_min = DMABRG_PERIOD_MIN,
98*4882a593Smuzhiyun .period_bytes_max = DMABRG_PERIOD_MAX / 2,
99*4882a593Smuzhiyun .periods_min = 2,
100*4882a593Smuzhiyun .periods_max = 2,
101*4882a593Smuzhiyun .fifo_size = 128,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
camelot_txdma(void * data)104*4882a593Smuzhiyun static void camelot_txdma(void *data)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun struct camelot_pcm *cam = data;
107*4882a593Smuzhiyun cam->tx_period ^= 1;
108*4882a593Smuzhiyun snd_pcm_period_elapsed(cam->tx_ss);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
camelot_rxdma(void * data)111*4882a593Smuzhiyun static void camelot_rxdma(void *data)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct camelot_pcm *cam = data;
114*4882a593Smuzhiyun cam->rx_period ^= 1;
115*4882a593Smuzhiyun snd_pcm_period_elapsed(cam->rx_ss);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
camelot_pcm_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)118*4882a593Smuzhiyun static int camelot_pcm_open(struct snd_soc_component *component,
119*4882a593Smuzhiyun struct snd_pcm_substream *substream)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
122*4882a593Smuzhiyun struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
123*4882a593Smuzhiyun int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
124*4882a593Smuzhiyun int ret, dmairq;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun snd_soc_set_runtime_hwparams(substream, &camelot_pcm_hardware);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* DMABRG buffer half/full events */
129*4882a593Smuzhiyun dmairq = (recv) ? cam->txid + 2 : cam->txid;
130*4882a593Smuzhiyun if (recv) {
131*4882a593Smuzhiyun cam->rx_ss = substream;
132*4882a593Smuzhiyun ret = dmabrg_request_irq(dmairq, camelot_rxdma, cam);
133*4882a593Smuzhiyun if (unlikely(ret)) {
134*4882a593Smuzhiyun pr_debug("audio unit %d irqs already taken!\n",
135*4882a593Smuzhiyun asoc_rtd_to_cpu(rtd, 0)->id);
136*4882a593Smuzhiyun return -EBUSY;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun (void)dmabrg_request_irq(dmairq + 1,camelot_rxdma, cam);
139*4882a593Smuzhiyun } else {
140*4882a593Smuzhiyun cam->tx_ss = substream;
141*4882a593Smuzhiyun ret = dmabrg_request_irq(dmairq, camelot_txdma, cam);
142*4882a593Smuzhiyun if (unlikely(ret)) {
143*4882a593Smuzhiyun pr_debug("audio unit %d irqs already taken!\n",
144*4882a593Smuzhiyun asoc_rtd_to_cpu(rtd, 0)->id);
145*4882a593Smuzhiyun return -EBUSY;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun (void)dmabrg_request_irq(dmairq + 1, camelot_txdma, cam);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun return 0;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
camelot_pcm_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)152*4882a593Smuzhiyun static int camelot_pcm_close(struct snd_soc_component *component,
153*4882a593Smuzhiyun struct snd_pcm_substream *substream)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
156*4882a593Smuzhiyun struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
157*4882a593Smuzhiyun int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
158*4882a593Smuzhiyun int dmairq;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun dmairq = (recv) ? cam->txid + 2 : cam->txid;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun if (recv)
163*4882a593Smuzhiyun cam->rx_ss = NULL;
164*4882a593Smuzhiyun else
165*4882a593Smuzhiyun cam->tx_ss = NULL;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun dmabrg_free_irq(dmairq + 1);
168*4882a593Smuzhiyun dmabrg_free_irq(dmairq);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun return 0;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
camelot_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)173*4882a593Smuzhiyun static int camelot_hw_params(struct snd_soc_component *component,
174*4882a593Smuzhiyun struct snd_pcm_substream *substream,
175*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
178*4882a593Smuzhiyun struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
179*4882a593Smuzhiyun int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
180*4882a593Smuzhiyun int ret;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun if (recv) {
183*4882a593Smuzhiyun cam->rx_period_size = params_period_bytes(hw_params);
184*4882a593Smuzhiyun cam->rx_period = 0;
185*4882a593Smuzhiyun } else {
186*4882a593Smuzhiyun cam->tx_period_size = params_period_bytes(hw_params);
187*4882a593Smuzhiyun cam->tx_period = 0;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
camelot_prepare(struct snd_soc_component * component,struct snd_pcm_substream * substream)192*4882a593Smuzhiyun static int camelot_prepare(struct snd_soc_component *component,
193*4882a593Smuzhiyun struct snd_pcm_substream *substream)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
196*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
197*4882a593Smuzhiyun struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun pr_debug("PCM data: addr 0x%08lx len %d\n",
200*4882a593Smuzhiyun (u32)runtime->dma_addr, runtime->dma_bytes);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
203*4882a593Smuzhiyun BRGREG(BRGATXSAR) = (unsigned long)runtime->dma_area;
204*4882a593Smuzhiyun BRGREG(BRGATXTCR) = runtime->dma_bytes;
205*4882a593Smuzhiyun } else {
206*4882a593Smuzhiyun BRGREG(BRGARXDAR) = (unsigned long)runtime->dma_area;
207*4882a593Smuzhiyun BRGREG(BRGARXTCR) = runtime->dma_bytes;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun return 0;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
dmabrg_play_dma_start(struct camelot_pcm * cam)213*4882a593Smuzhiyun static inline void dmabrg_play_dma_start(struct camelot_pcm *cam)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
216*4882a593Smuzhiyun /* start DMABRG engine: XFER start, auto-addr-reload */
217*4882a593Smuzhiyun BRGREG(BRGACR) = acr | ACR_TDE | ACR_TAR | ACR_TAM_2WORD;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
dmabrg_play_dma_stop(struct camelot_pcm * cam)220*4882a593Smuzhiyun static inline void dmabrg_play_dma_stop(struct camelot_pcm *cam)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
223*4882a593Smuzhiyun /* forcibly terminate data transmission */
224*4882a593Smuzhiyun BRGREG(BRGACR) = acr | ACR_TDS;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
dmabrg_rec_dma_start(struct camelot_pcm * cam)227*4882a593Smuzhiyun static inline void dmabrg_rec_dma_start(struct camelot_pcm *cam)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
230*4882a593Smuzhiyun /* start DMABRG engine: recv start, auto-reload */
231*4882a593Smuzhiyun BRGREG(BRGACR) = acr | ACR_RDE | ACR_RAR | ACR_RAM_2WORD;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
dmabrg_rec_dma_stop(struct camelot_pcm * cam)234*4882a593Smuzhiyun static inline void dmabrg_rec_dma_stop(struct camelot_pcm *cam)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
237*4882a593Smuzhiyun /* forcibly terminate data receiver */
238*4882a593Smuzhiyun BRGREG(BRGACR) = acr | ACR_RDS;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
camelot_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)241*4882a593Smuzhiyun static int camelot_trigger(struct snd_soc_component *component,
242*4882a593Smuzhiyun struct snd_pcm_substream *substream, int cmd)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
245*4882a593Smuzhiyun struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
246*4882a593Smuzhiyun int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun switch (cmd) {
249*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
250*4882a593Smuzhiyun if (recv)
251*4882a593Smuzhiyun dmabrg_rec_dma_start(cam);
252*4882a593Smuzhiyun else
253*4882a593Smuzhiyun dmabrg_play_dma_start(cam);
254*4882a593Smuzhiyun break;
255*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
256*4882a593Smuzhiyun if (recv)
257*4882a593Smuzhiyun dmabrg_rec_dma_stop(cam);
258*4882a593Smuzhiyun else
259*4882a593Smuzhiyun dmabrg_play_dma_stop(cam);
260*4882a593Smuzhiyun break;
261*4882a593Smuzhiyun default:
262*4882a593Smuzhiyun return -EINVAL;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun return 0;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
camelot_pos(struct snd_soc_component * component,struct snd_pcm_substream * substream)268*4882a593Smuzhiyun static snd_pcm_uframes_t camelot_pos(struct snd_soc_component *component,
269*4882a593Smuzhiyun struct snd_pcm_substream *substream)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
272*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
273*4882a593Smuzhiyun struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
274*4882a593Smuzhiyun int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
275*4882a593Smuzhiyun unsigned long pos;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun /* cannot use the DMABRG pointer register: under load, by the
278*4882a593Smuzhiyun * time ALSA comes around to read the register, it is already
279*4882a593Smuzhiyun * far ahead (or worse, already done with the fragment) of the
280*4882a593Smuzhiyun * position at the time the IRQ was triggered, which results in
281*4882a593Smuzhiyun * fast-playback sound in my test application (ScummVM)
282*4882a593Smuzhiyun */
283*4882a593Smuzhiyun if (recv)
284*4882a593Smuzhiyun pos = cam->rx_period ? cam->rx_period_size : 0;
285*4882a593Smuzhiyun else
286*4882a593Smuzhiyun pos = cam->tx_period ? cam->tx_period_size : 0;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun return bytes_to_frames(runtime, pos);
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
camelot_pcm_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)291*4882a593Smuzhiyun static int camelot_pcm_new(struct snd_soc_component *component,
292*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun struct snd_pcm *pcm = rtd->pcm;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun /* dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
297*4882a593Smuzhiyun * in MMAP mode (i.e. aplay -M)
298*4882a593Smuzhiyun */
299*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm,
300*4882a593Smuzhiyun SNDRV_DMA_TYPE_CONTINUOUS,
301*4882a593Smuzhiyun NULL,
302*4882a593Smuzhiyun DMABRG_PREALLOC_BUFFER, DMABRG_PREALLOC_BUFFER_MAX);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun return 0;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun static const struct snd_soc_component_driver sh7760_soc_component = {
308*4882a593Smuzhiyun .open = camelot_pcm_open,
309*4882a593Smuzhiyun .close = camelot_pcm_close,
310*4882a593Smuzhiyun .hw_params = camelot_hw_params,
311*4882a593Smuzhiyun .prepare = camelot_prepare,
312*4882a593Smuzhiyun .trigger = camelot_trigger,
313*4882a593Smuzhiyun .pointer = camelot_pos,
314*4882a593Smuzhiyun .pcm_construct = camelot_pcm_new,
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun
sh7760_soc_platform_probe(struct platform_device * pdev)317*4882a593Smuzhiyun static int sh7760_soc_platform_probe(struct platform_device *pdev)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun return devm_snd_soc_register_component(&pdev->dev, &sh7760_soc_component,
320*4882a593Smuzhiyun NULL, 0);
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun static struct platform_driver sh7760_pcm_driver = {
324*4882a593Smuzhiyun .driver = {
325*4882a593Smuzhiyun .name = "sh7760-pcm-audio",
326*4882a593Smuzhiyun },
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun .probe = sh7760_soc_platform_probe,
329*4882a593Smuzhiyun };
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun module_platform_driver(sh7760_pcm_driver);
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
334*4882a593Smuzhiyun MODULE_DESCRIPTION("SH7760 Audio DMA (DMABRG) driver");
335*4882a593Smuzhiyun MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");
336