1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Modifications by Christian Pellegrin <chripell@evolware.org>
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // s3c24xx_uda134x.c - S3C24XX_UDA134X ALSA SoC Audio board driver
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun // Copyright 2007 Dension Audio Systems Ltd.
8*4882a593Smuzhiyun // Author: Zoltan Devai
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/gpio.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <sound/soc.h>
15*4882a593Smuzhiyun #include <sound/s3c24xx_uda134x.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "regs-iis.h"
18*4882a593Smuzhiyun #include "s3c24xx-i2s.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct s3c24xx_uda134x {
21*4882a593Smuzhiyun struct clk *xtal;
22*4882a593Smuzhiyun struct clk *pclk;
23*4882a593Smuzhiyun struct mutex clk_lock;
24*4882a593Smuzhiyun int clk_users;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* #define ENFORCE_RATES 1 */
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun Unfortunately the S3C24XX in master mode has a limited capacity of
30*4882a593Smuzhiyun generating the clock for the codec. If you define this only rates
31*4882a593Smuzhiyun that are really available will be enforced. But be careful, most
32*4882a593Smuzhiyun user level application just want the usual sampling frequencies (8,
33*4882a593Smuzhiyun 11.025, 22.050, 44.1 kHz) and anyway resampling is a costly
34*4882a593Smuzhiyun operation for embedded systems. So if you aren't very lucky or your
35*4882a593Smuzhiyun hardware engineer wasn't very forward-looking it's better to leave
36*4882a593Smuzhiyun this undefined. If you do so an approximate value for the requested
37*4882a593Smuzhiyun sampling rate in the range -/+ 5% will be chosen. If this in not
38*4882a593Smuzhiyun possible an error will be returned.
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static unsigned int rates[33 * 2];
42*4882a593Smuzhiyun #ifdef ENFORCE_RATES
43*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
44*4882a593Smuzhiyun .count = ARRAY_SIZE(rates),
45*4882a593Smuzhiyun .list = rates,
46*4882a593Smuzhiyun .mask = 0,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun #endif
49*4882a593Smuzhiyun
s3c24xx_uda134x_startup(struct snd_pcm_substream * substream)50*4882a593Smuzhiyun static int s3c24xx_uda134x_startup(struct snd_pcm_substream *substream)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
53*4882a593Smuzhiyun struct s3c24xx_uda134x *priv = snd_soc_card_get_drvdata(rtd->card);
54*4882a593Smuzhiyun struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
55*4882a593Smuzhiyun int ret = 0;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun mutex_lock(&priv->clk_lock);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (priv->clk_users == 0) {
60*4882a593Smuzhiyun priv->xtal = clk_get(rtd->dev, "xtal");
61*4882a593Smuzhiyun if (IS_ERR(priv->xtal)) {
62*4882a593Smuzhiyun dev_err(rtd->dev, "%s cannot get xtal\n", __func__);
63*4882a593Smuzhiyun ret = PTR_ERR(priv->xtal);
64*4882a593Smuzhiyun } else {
65*4882a593Smuzhiyun priv->pclk = clk_get(cpu_dai->dev, "iis");
66*4882a593Smuzhiyun if (IS_ERR(priv->pclk)) {
67*4882a593Smuzhiyun dev_err(rtd->dev, "%s cannot get pclk\n",
68*4882a593Smuzhiyun __func__);
69*4882a593Smuzhiyun clk_put(priv->xtal);
70*4882a593Smuzhiyun ret = PTR_ERR(priv->pclk);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun if (!ret) {
74*4882a593Smuzhiyun int i, j;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
77*4882a593Smuzhiyun int fs = i ? 256 : 384;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun rates[i*33] = clk_get_rate(priv->xtal) / fs;
80*4882a593Smuzhiyun for (j = 1; j < 33; j++)
81*4882a593Smuzhiyun rates[i*33 + j] = clk_get_rate(priv->pclk) /
82*4882a593Smuzhiyun (j * fs);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun priv->clk_users += 1;
87*4882a593Smuzhiyun mutex_unlock(&priv->clk_lock);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (!ret) {
90*4882a593Smuzhiyun #ifdef ENFORCE_RATES
91*4882a593Smuzhiyun ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
92*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE,
93*4882a593Smuzhiyun &hw_constraints_rates);
94*4882a593Smuzhiyun if (ret < 0)
95*4882a593Smuzhiyun dev_err(rtd->dev, "%s cannot set constraints\n",
96*4882a593Smuzhiyun __func__);
97*4882a593Smuzhiyun #endif
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun return ret;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
s3c24xx_uda134x_shutdown(struct snd_pcm_substream * substream)102*4882a593Smuzhiyun static void s3c24xx_uda134x_shutdown(struct snd_pcm_substream *substream)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
105*4882a593Smuzhiyun struct s3c24xx_uda134x *priv = snd_soc_card_get_drvdata(rtd->card);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun mutex_lock(&priv->clk_lock);
108*4882a593Smuzhiyun priv->clk_users -= 1;
109*4882a593Smuzhiyun if (priv->clk_users == 0) {
110*4882a593Smuzhiyun clk_put(priv->xtal);
111*4882a593Smuzhiyun priv->xtal = NULL;
112*4882a593Smuzhiyun clk_put(priv->pclk);
113*4882a593Smuzhiyun priv->pclk = NULL;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun mutex_unlock(&priv->clk_lock);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
s3c24xx_uda134x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)118*4882a593Smuzhiyun static int s3c24xx_uda134x_hw_params(struct snd_pcm_substream *substream,
119*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
122*4882a593Smuzhiyun struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
123*4882a593Smuzhiyun struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
124*4882a593Smuzhiyun unsigned int clk = 0;
125*4882a593Smuzhiyun int ret = 0;
126*4882a593Smuzhiyun int clk_source, fs_mode;
127*4882a593Smuzhiyun unsigned long rate = params_rate(params);
128*4882a593Smuzhiyun long err, cerr;
129*4882a593Smuzhiyun unsigned int div;
130*4882a593Smuzhiyun int i, bi;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun err = 999999;
133*4882a593Smuzhiyun bi = 0;
134*4882a593Smuzhiyun for (i = 0; i < 2*33; i++) {
135*4882a593Smuzhiyun cerr = rates[i] - rate;
136*4882a593Smuzhiyun if (cerr < 0)
137*4882a593Smuzhiyun cerr = -cerr;
138*4882a593Smuzhiyun if (cerr < err) {
139*4882a593Smuzhiyun err = cerr;
140*4882a593Smuzhiyun bi = i;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun if (bi / 33 == 1)
144*4882a593Smuzhiyun fs_mode = S3C2410_IISMOD_256FS;
145*4882a593Smuzhiyun else
146*4882a593Smuzhiyun fs_mode = S3C2410_IISMOD_384FS;
147*4882a593Smuzhiyun if (bi % 33 == 0) {
148*4882a593Smuzhiyun clk_source = S3C24XX_CLKSRC_MPLL;
149*4882a593Smuzhiyun div = 1;
150*4882a593Smuzhiyun } else {
151*4882a593Smuzhiyun clk_source = S3C24XX_CLKSRC_PCLK;
152*4882a593Smuzhiyun div = bi % 33;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun dev_dbg(rtd->dev, "%s desired rate %lu, %d\n", __func__, rate, bi);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun clk = (fs_mode == S3C2410_IISMOD_384FS ? 384 : 256) * rate;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun dev_dbg(rtd->dev, "%s will use: %s %s %d sysclk %d err %ld\n", __func__,
160*4882a593Smuzhiyun fs_mode == S3C2410_IISMOD_384FS ? "384FS" : "256FS",
161*4882a593Smuzhiyun clk_source == S3C24XX_CLKSRC_MPLL ? "MPLLin" : "PCLK",
162*4882a593Smuzhiyun div, clk, err);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun if ((err * 100 / rate) > 5) {
165*4882a593Smuzhiyun dev_err(rtd->dev, "effective frequency too different "
166*4882a593Smuzhiyun "from desired (%ld%%)\n", err * 100 / rate);
167*4882a593Smuzhiyun return -EINVAL;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun ret = snd_soc_dai_set_sysclk(cpu_dai, clk_source , clk,
171*4882a593Smuzhiyun SND_SOC_CLOCK_IN);
172*4882a593Smuzhiyun if (ret < 0)
173*4882a593Smuzhiyun return ret;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK, fs_mode);
176*4882a593Smuzhiyun if (ret < 0)
177*4882a593Smuzhiyun return ret;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_BCLK,
180*4882a593Smuzhiyun S3C2410_IISMOD_32FS);
181*4882a593Smuzhiyun if (ret < 0)
182*4882a593Smuzhiyun return ret;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
185*4882a593Smuzhiyun S3C24XX_PRESCALE(div, div));
186*4882a593Smuzhiyun if (ret < 0)
187*4882a593Smuzhiyun return ret;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* set the codec system clock for DAC and ADC */
190*4882a593Smuzhiyun ret = snd_soc_dai_set_sysclk(codec_dai, 0, clk,
191*4882a593Smuzhiyun SND_SOC_CLOCK_OUT);
192*4882a593Smuzhiyun if (ret < 0)
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun return 0;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun static const struct snd_soc_ops s3c24xx_uda134x_ops = {
199*4882a593Smuzhiyun .startup = s3c24xx_uda134x_startup,
200*4882a593Smuzhiyun .shutdown = s3c24xx_uda134x_shutdown,
201*4882a593Smuzhiyun .hw_params = s3c24xx_uda134x_hw_params,
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun SND_SOC_DAILINK_DEFS(uda134x,
205*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("s3c24xx-iis")),
206*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("uda134x-codec", "uda134x-hifi")),
207*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_PLATFORM("s3c24xx-iis")));
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun static struct snd_soc_dai_link s3c24xx_uda134x_dai_link = {
210*4882a593Smuzhiyun .name = "UDA134X",
211*4882a593Smuzhiyun .stream_name = "UDA134X",
212*4882a593Smuzhiyun .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
213*4882a593Smuzhiyun SND_SOC_DAIFMT_CBS_CFS,
214*4882a593Smuzhiyun .ops = &s3c24xx_uda134x_ops,
215*4882a593Smuzhiyun SND_SOC_DAILINK_REG(uda134x),
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun static struct snd_soc_card snd_soc_s3c24xx_uda134x = {
219*4882a593Smuzhiyun .name = "S3C24XX_UDA134X",
220*4882a593Smuzhiyun .owner = THIS_MODULE,
221*4882a593Smuzhiyun .dai_link = &s3c24xx_uda134x_dai_link,
222*4882a593Smuzhiyun .num_links = 1,
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun
s3c24xx_uda134x_probe(struct platform_device * pdev)225*4882a593Smuzhiyun static int s3c24xx_uda134x_probe(struct platform_device *pdev)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun struct snd_soc_card *card = &snd_soc_s3c24xx_uda134x;
228*4882a593Smuzhiyun struct s3c24xx_uda134x *priv;
229*4882a593Smuzhiyun int ret;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
232*4882a593Smuzhiyun if (!priv)
233*4882a593Smuzhiyun return -ENOMEM;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun mutex_init(&priv->clk_lock);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun card->dev = &pdev->dev;
238*4882a593Smuzhiyun snd_soc_card_set_drvdata(card, priv);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun ret = devm_snd_soc_register_card(&pdev->dev, card);
241*4882a593Smuzhiyun if (ret)
242*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to register card: %d\n", ret);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun return ret;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun static struct platform_driver s3c24xx_uda134x_driver = {
248*4882a593Smuzhiyun .probe = s3c24xx_uda134x_probe,
249*4882a593Smuzhiyun .driver = {
250*4882a593Smuzhiyun .name = "s3c24xx_uda134x",
251*4882a593Smuzhiyun },
252*4882a593Smuzhiyun };
253*4882a593Smuzhiyun module_platform_driver(s3c24xx_uda134x_driver);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
256*4882a593Smuzhiyun MODULE_DESCRIPTION("S3C24XX_UDA134X ALSA SoC audio driver");
257*4882a593Smuzhiyun MODULE_LICENSE("GPL");
258