1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * s3c24xx-i2s.c -- ALSA Soc Audio Layer 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2005 Wolfson Microelectronics PLC. 6*4882a593Smuzhiyun * Author: Graeme Gregory 7*4882a593Smuzhiyun * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Revision history 10*4882a593Smuzhiyun * 10th Nov 2006 Initial version. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef S3C24XXI2S_H_ 14*4882a593Smuzhiyun #define S3C24XXI2S_H_ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* clock sources */ 17*4882a593Smuzhiyun #define S3C24XX_CLKSRC_PCLK 0 18*4882a593Smuzhiyun #define S3C24XX_CLKSRC_MPLL 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Clock dividers */ 21*4882a593Smuzhiyun #define S3C24XX_DIV_MCLK 0 22*4882a593Smuzhiyun #define S3C24XX_DIV_BCLK 1 23*4882a593Smuzhiyun #define S3C24XX_DIV_PRESCALER 2 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* prescaler */ 26*4882a593Smuzhiyun #define S3C24XX_PRESCALE(a,b) \ 27*4882a593Smuzhiyun (((a - 1) << S3C2410_IISPSR_INTSHIFT) | ((b - 1) << S3C2410_IISPSR_EXTSHFIT)) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun u32 s3c24xx_i2s_get_clockrate(void); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif /*S3C24XXI2S_H_*/ 32