1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2007 Simtec Electronics <linux@simtec.co.uk> 4*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * S3C2412 IIS register definition 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_REGS_S3C2412_IIS_H 10*4882a593Smuzhiyun #define __ASM_ARCH_REGS_S3C2412_IIS_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define S3C2412_IISCON (0x00) 13*4882a593Smuzhiyun #define S3C2412_IISMOD (0x04) 14*4882a593Smuzhiyun #define S3C2412_IISFIC (0x08) 15*4882a593Smuzhiyun #define S3C2412_IISPSR (0x0C) 16*4882a593Smuzhiyun #define S3C2412_IISTXD (0x10) 17*4882a593Smuzhiyun #define S3C2412_IISRXD (0x14) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define S5PC1XX_IISFICS 0x18 20*4882a593Smuzhiyun #define S5PC1XX_IISTXDS 0x1C 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define S5PC1XX_IISCON_SW_RST (1 << 31) 23*4882a593Smuzhiyun #define S5PC1XX_IISCON_FRXOFSTATUS (1 << 26) 24*4882a593Smuzhiyun #define S5PC1XX_IISCON_FRXORINTEN (1 << 25) 25*4882a593Smuzhiyun #define S5PC1XX_IISCON_FTXSURSTAT (1 << 24) 26*4882a593Smuzhiyun #define S5PC1XX_IISCON_FTXSURINTEN (1 << 23) 27*4882a593Smuzhiyun #define S5PC1XX_IISCON_TXSDMAPAUSE (1 << 20) 28*4882a593Smuzhiyun #define S5PC1XX_IISCON_TXSDMACTIVE (1 << 18) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define S3C64XX_IISCON_FTXURSTATUS (1 << 17) 31*4882a593Smuzhiyun #define S3C64XX_IISCON_FTXURINTEN (1 << 16) 32*4882a593Smuzhiyun #define S3C64XX_IISCON_TXFIFO2_EMPTY (1 << 15) 33*4882a593Smuzhiyun #define S3C64XX_IISCON_TXFIFO1_EMPTY (1 << 14) 34*4882a593Smuzhiyun #define S3C64XX_IISCON_TXFIFO2_FULL (1 << 13) 35*4882a593Smuzhiyun #define S3C64XX_IISCON_TXFIFO1_FULL (1 << 12) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define S3C2412_IISCON_LRINDEX (1 << 11) 38*4882a593Smuzhiyun #define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10) 39*4882a593Smuzhiyun #define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9) 40*4882a593Smuzhiyun #define S3C2412_IISCON_TXFIFO_FULL (1 << 8) 41*4882a593Smuzhiyun #define S3C2412_IISCON_RXFIFO_FULL (1 << 7) 42*4882a593Smuzhiyun #define S3C2412_IISCON_TXDMA_PAUSE (1 << 6) 43*4882a593Smuzhiyun #define S3C2412_IISCON_RXDMA_PAUSE (1 << 5) 44*4882a593Smuzhiyun #define S3C2412_IISCON_TXCH_PAUSE (1 << 4) 45*4882a593Smuzhiyun #define S3C2412_IISCON_RXCH_PAUSE (1 << 3) 46*4882a593Smuzhiyun #define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2) 47*4882a593Smuzhiyun #define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1) 48*4882a593Smuzhiyun #define S3C2412_IISCON_IIS_ACTIVE (1 << 0) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define S5PC1XX_IISMOD_OPCLK_CDCLK_OUT (0 << 30) 51*4882a593Smuzhiyun #define S5PC1XX_IISMOD_OPCLK_CDCLK_IN (1 << 30) 52*4882a593Smuzhiyun #define S5PC1XX_IISMOD_OPCLK_BCLK_OUT (2 << 30) 53*4882a593Smuzhiyun #define S5PC1XX_IISMOD_OPCLK_PCLK (3 << 30) 54*4882a593Smuzhiyun #define S5PC1XX_IISMOD_OPCLK_MASK (3 << 30) 55*4882a593Smuzhiyun #define S5PC1XX_IISMOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */ 56*4882a593Smuzhiyun #define S5PC1XX_IISMOD_BLCS_MASK 0x3 57*4882a593Smuzhiyun #define S5PC1XX_IISMOD_BLCS_SHIFT 26 58*4882a593Smuzhiyun #define S5PC1XX_IISMOD_BLCP_MASK 0x3 59*4882a593Smuzhiyun #define S5PC1XX_IISMOD_BLCP_SHIFT 24 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define S3C64XX_IISMOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */ 62*4882a593Smuzhiyun #define S3C64XX_IISMOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */ 63*4882a593Smuzhiyun #define S3C64XX_IISMOD_C1DD_HHALF (1 << 19) 64*4882a593Smuzhiyun #define S3C64XX_IISMOD_C1DD_LHALF (1 << 18) 65*4882a593Smuzhiyun #define S3C64XX_IISMOD_DC2_EN (1 << 17) 66*4882a593Smuzhiyun #define S3C64XX_IISMOD_DC1_EN (1 << 16) 67*4882a593Smuzhiyun #define S3C64XX_IISMOD_BLC_16BIT (0 << 13) 68*4882a593Smuzhiyun #define S3C64XX_IISMOD_BLC_8BIT (1 << 13) 69*4882a593Smuzhiyun #define S3C64XX_IISMOD_BLC_24BIT (2 << 13) 70*4882a593Smuzhiyun #define S3C64XX_IISMOD_BLC_MASK (3 << 13) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define S3C2412_IISMOD_IMS_SYSMUX (1 << 10) 73*4882a593Smuzhiyun #define S3C2412_IISMOD_SLAVE (1 << 11) 74*4882a593Smuzhiyun #define S3C2412_IISMOD_MODE_TXONLY (0 << 8) 75*4882a593Smuzhiyun #define S3C2412_IISMOD_MODE_RXONLY (1 << 8) 76*4882a593Smuzhiyun #define S3C2412_IISMOD_MODE_TXRX (2 << 8) 77*4882a593Smuzhiyun #define S3C2412_IISMOD_MODE_MASK (3 << 8) 78*4882a593Smuzhiyun #define S3C2412_IISMOD_LR_LLOW (0 << 7) 79*4882a593Smuzhiyun #define S3C2412_IISMOD_LR_RLOW (1 << 7) 80*4882a593Smuzhiyun #define S3C2412_IISMOD_SDF_IIS (0 << 5) 81*4882a593Smuzhiyun #define S3C2412_IISMOD_SDF_MSB (1 << 5) 82*4882a593Smuzhiyun #define S3C2412_IISMOD_SDF_LSB (2 << 5) 83*4882a593Smuzhiyun #define S3C2412_IISMOD_SDF_MASK (3 << 5) 84*4882a593Smuzhiyun #define S3C2412_IISMOD_RCLK_256FS (0 << 3) 85*4882a593Smuzhiyun #define S3C2412_IISMOD_RCLK_512FS (1 << 3) 86*4882a593Smuzhiyun #define S3C2412_IISMOD_RCLK_384FS (2 << 3) 87*4882a593Smuzhiyun #define S3C2412_IISMOD_RCLK_768FS (3 << 3) 88*4882a593Smuzhiyun #define S3C2412_IISMOD_RCLK_MASK (3 << 3) 89*4882a593Smuzhiyun #define S3C2412_IISMOD_BCLK_32FS (0 << 1) 90*4882a593Smuzhiyun #define S3C2412_IISMOD_BCLK_48FS (1 << 1) 91*4882a593Smuzhiyun #define S3C2412_IISMOD_BCLK_16FS (2 << 1) 92*4882a593Smuzhiyun #define S3C2412_IISMOD_BCLK_24FS (3 << 1) 93*4882a593Smuzhiyun #define S3C2412_IISMOD_BCLK_MASK (3 << 1) 94*4882a593Smuzhiyun #define S3C2412_IISMOD_8BIT (1 << 0) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define S3C64XX_IISMOD_CDCLKCON (1 << 12) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define S3C2412_IISPSR_PSREN (1 << 15) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define S3C64XX_IISFIC_TX2COUNT(x) (((x) >> 24) & 0xf) 101*4882a593Smuzhiyun #define S3C64XX_IISFIC_TX1COUNT(x) (((x) >> 16) & 0xf) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define S3C2412_IISFIC_TXFLUSH (1 << 15) 104*4882a593Smuzhiyun #define S3C2412_IISFIC_RXFLUSH (1 << 7) 105*4882a593Smuzhiyun #define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf) 106*4882a593Smuzhiyun #define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define S5PC1XX_IISFICS_TXFLUSH (1 << 15) 109*4882a593Smuzhiyun #define S5PC1XX_IISFICS_TXCOUNT(x) (((x) >> 8) & 0x7f) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */ 112