1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // idma.c - I2S0 internal DMA driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2011 Samsung Electronics Co., Ltd.
6*4882a593Smuzhiyun // http://www.samsung.com
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/interrupt.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/dma-mapping.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <sound/pcm.h>
14*4882a593Smuzhiyun #include <sound/pcm_params.h>
15*4882a593Smuzhiyun #include <sound/soc.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "i2s.h"
18*4882a593Smuzhiyun #include "idma.h"
19*4882a593Smuzhiyun #include "i2s-regs.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define ST_RUNNING (1<<0)
22*4882a593Smuzhiyun #define ST_OPENED (1<<1)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static const struct snd_pcm_hardware idma_hardware = {
25*4882a593Smuzhiyun .info = SNDRV_PCM_INFO_INTERLEAVED |
26*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
27*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP |
28*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
29*4882a593Smuzhiyun SNDRV_PCM_INFO_PAUSE |
30*4882a593Smuzhiyun SNDRV_PCM_INFO_RESUME,
31*4882a593Smuzhiyun .buffer_bytes_max = MAX_IDMA_BUFFER,
32*4882a593Smuzhiyun .period_bytes_min = 128,
33*4882a593Smuzhiyun .period_bytes_max = MAX_IDMA_PERIOD,
34*4882a593Smuzhiyun .periods_min = 1,
35*4882a593Smuzhiyun .periods_max = 2,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun struct idma_ctrl {
39*4882a593Smuzhiyun spinlock_t lock;
40*4882a593Smuzhiyun int state;
41*4882a593Smuzhiyun dma_addr_t start;
42*4882a593Smuzhiyun dma_addr_t pos;
43*4882a593Smuzhiyun dma_addr_t end;
44*4882a593Smuzhiyun dma_addr_t period;
45*4882a593Smuzhiyun dma_addr_t periodsz;
46*4882a593Smuzhiyun void *token;
47*4882a593Smuzhiyun void (*cb)(void *dt, int bytes_xfer);
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static struct idma_info {
51*4882a593Smuzhiyun spinlock_t lock;
52*4882a593Smuzhiyun void __iomem *regs;
53*4882a593Smuzhiyun dma_addr_t lp_tx_addr;
54*4882a593Smuzhiyun } idma;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static int idma_irq;
57*4882a593Smuzhiyun
idma_getpos(dma_addr_t * src)58*4882a593Smuzhiyun static void idma_getpos(dma_addr_t *src)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun *src = idma.lp_tx_addr +
61*4882a593Smuzhiyun (readl(idma.regs + I2STRNCNT) & 0xffffff) * 4;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
idma_enqueue(struct snd_pcm_substream * substream)64*4882a593Smuzhiyun static int idma_enqueue(struct snd_pcm_substream *substream)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
67*4882a593Smuzhiyun struct idma_ctrl *prtd = substream->runtime->private_data;
68*4882a593Smuzhiyun u32 val;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun spin_lock(&prtd->lock);
71*4882a593Smuzhiyun prtd->token = (void *) substream;
72*4882a593Smuzhiyun spin_unlock(&prtd->lock);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Internal DMA Level0 Interrupt Address */
75*4882a593Smuzhiyun val = idma.lp_tx_addr + prtd->periodsz;
76*4882a593Smuzhiyun writel(val, idma.regs + I2SLVL0ADDR);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Start address0 of I2S internal DMA operation. */
79*4882a593Smuzhiyun val = idma.lp_tx_addr;
80*4882a593Smuzhiyun writel(val, idma.regs + I2SSTR0);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * Transfer block size for I2S internal DMA.
84*4882a593Smuzhiyun * Should decide transfer size before start dma operation
85*4882a593Smuzhiyun */
86*4882a593Smuzhiyun val = readl(idma.regs + I2SSIZE);
87*4882a593Smuzhiyun val &= ~(I2SSIZE_TRNMSK << I2SSIZE_SHIFT);
88*4882a593Smuzhiyun val |= (((runtime->dma_bytes >> 2) &
89*4882a593Smuzhiyun I2SSIZE_TRNMSK) << I2SSIZE_SHIFT);
90*4882a593Smuzhiyun writel(val, idma.regs + I2SSIZE);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun val = readl(idma.regs + I2SAHB);
93*4882a593Smuzhiyun val |= AHB_INTENLVL0;
94*4882a593Smuzhiyun writel(val, idma.regs + I2SAHB);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
idma_setcallbk(struct snd_pcm_substream * substream,void (* cb)(void *,int))99*4882a593Smuzhiyun static void idma_setcallbk(struct snd_pcm_substream *substream,
100*4882a593Smuzhiyun void (*cb)(void *, int))
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun struct idma_ctrl *prtd = substream->runtime->private_data;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun spin_lock(&prtd->lock);
105*4882a593Smuzhiyun prtd->cb = cb;
106*4882a593Smuzhiyun spin_unlock(&prtd->lock);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
idma_control(int op)109*4882a593Smuzhiyun static void idma_control(int op)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun u32 val = readl(idma.regs + I2SAHB);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun spin_lock(&idma.lock);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun switch (op) {
116*4882a593Smuzhiyun case LPAM_DMA_START:
117*4882a593Smuzhiyun val |= (AHB_INTENLVL0 | AHB_DMAEN);
118*4882a593Smuzhiyun break;
119*4882a593Smuzhiyun case LPAM_DMA_STOP:
120*4882a593Smuzhiyun val &= ~(AHB_INTENLVL0 | AHB_DMAEN);
121*4882a593Smuzhiyun break;
122*4882a593Smuzhiyun default:
123*4882a593Smuzhiyun spin_unlock(&idma.lock);
124*4882a593Smuzhiyun return;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun writel(val, idma.regs + I2SAHB);
128*4882a593Smuzhiyun spin_unlock(&idma.lock);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
idma_done(void * id,int bytes_xfer)131*4882a593Smuzhiyun static void idma_done(void *id, int bytes_xfer)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun struct snd_pcm_substream *substream = id;
134*4882a593Smuzhiyun struct idma_ctrl *prtd = substream->runtime->private_data;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun if (prtd && (prtd->state & ST_RUNNING))
137*4882a593Smuzhiyun snd_pcm_period_elapsed(substream);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
idma_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)140*4882a593Smuzhiyun static int idma_hw_params(struct snd_soc_component *component,
141*4882a593Smuzhiyun struct snd_pcm_substream *substream,
142*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
145*4882a593Smuzhiyun struct idma_ctrl *prtd = substream->runtime->private_data;
146*4882a593Smuzhiyun u32 mod = readl(idma.regs + I2SMOD);
147*4882a593Smuzhiyun u32 ahb = readl(idma.regs + I2SAHB);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun ahb |= (AHB_DMARLD | AHB_INTMASK);
150*4882a593Smuzhiyun mod |= MOD_TXS_IDMA;
151*4882a593Smuzhiyun writel(ahb, idma.regs + I2SAHB);
152*4882a593Smuzhiyun writel(mod, idma.regs + I2SMOD);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
155*4882a593Smuzhiyun runtime->dma_bytes = params_buffer_bytes(params);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun prtd->start = prtd->pos = runtime->dma_addr;
158*4882a593Smuzhiyun prtd->period = params_periods(params);
159*4882a593Smuzhiyun prtd->periodsz = params_period_bytes(params);
160*4882a593Smuzhiyun prtd->end = runtime->dma_addr + runtime->dma_bytes;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun idma_setcallbk(substream, idma_done);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun return 0;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
idma_hw_free(struct snd_soc_component * component,struct snd_pcm_substream * substream)167*4882a593Smuzhiyun static int idma_hw_free(struct snd_soc_component *component,
168*4882a593Smuzhiyun struct snd_pcm_substream *substream)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun snd_pcm_set_runtime_buffer(substream, NULL);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun return 0;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
idma_prepare(struct snd_soc_component * component,struct snd_pcm_substream * substream)175*4882a593Smuzhiyun static int idma_prepare(struct snd_soc_component *component,
176*4882a593Smuzhiyun struct snd_pcm_substream *substream)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun struct idma_ctrl *prtd = substream->runtime->private_data;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun prtd->pos = prtd->start;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* flush the DMA channel */
183*4882a593Smuzhiyun idma_control(LPAM_DMA_STOP);
184*4882a593Smuzhiyun idma_enqueue(substream);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun return 0;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
idma_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)189*4882a593Smuzhiyun static int idma_trigger(struct snd_soc_component *component,
190*4882a593Smuzhiyun struct snd_pcm_substream *substream, int cmd)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun struct idma_ctrl *prtd = substream->runtime->private_data;
193*4882a593Smuzhiyun int ret = 0;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun spin_lock(&prtd->lock);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun switch (cmd) {
198*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
199*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
200*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
201*4882a593Smuzhiyun prtd->state |= ST_RUNNING;
202*4882a593Smuzhiyun idma_control(LPAM_DMA_START);
203*4882a593Smuzhiyun break;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
206*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
207*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
208*4882a593Smuzhiyun prtd->state &= ~ST_RUNNING;
209*4882a593Smuzhiyun idma_control(LPAM_DMA_STOP);
210*4882a593Smuzhiyun break;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun default:
213*4882a593Smuzhiyun ret = -EINVAL;
214*4882a593Smuzhiyun break;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun spin_unlock(&prtd->lock);
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun return ret;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun static snd_pcm_uframes_t
idma_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)223*4882a593Smuzhiyun idma_pointer(struct snd_soc_component *component,
224*4882a593Smuzhiyun struct snd_pcm_substream *substream)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
227*4882a593Smuzhiyun struct idma_ctrl *prtd = runtime->private_data;
228*4882a593Smuzhiyun dma_addr_t src;
229*4882a593Smuzhiyun unsigned long res;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun spin_lock(&prtd->lock);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun idma_getpos(&src);
234*4882a593Smuzhiyun res = src - prtd->start;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun spin_unlock(&prtd->lock);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun return bytes_to_frames(substream->runtime, res);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
idma_mmap(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct vm_area_struct * vma)241*4882a593Smuzhiyun static int idma_mmap(struct snd_soc_component *component,
242*4882a593Smuzhiyun struct snd_pcm_substream *substream,
243*4882a593Smuzhiyun struct vm_area_struct *vma)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
246*4882a593Smuzhiyun unsigned long size, offset;
247*4882a593Smuzhiyun int ret;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /* From snd_pcm_lib_mmap_iomem */
250*4882a593Smuzhiyun vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
251*4882a593Smuzhiyun size = vma->vm_end - vma->vm_start;
252*4882a593Smuzhiyun offset = vma->vm_pgoff << PAGE_SHIFT;
253*4882a593Smuzhiyun ret = io_remap_pfn_range(vma, vma->vm_start,
254*4882a593Smuzhiyun (runtime->dma_addr + offset) >> PAGE_SHIFT,
255*4882a593Smuzhiyun size, vma->vm_page_prot);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun return ret;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
iis_irq(int irqno,void * dev_id)260*4882a593Smuzhiyun static irqreturn_t iis_irq(int irqno, void *dev_id)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun struct idma_ctrl *prtd = (struct idma_ctrl *)dev_id;
263*4882a593Smuzhiyun u32 iisahb, val, addr;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun iisahb = readl(idma.regs + I2SAHB);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun val = (iisahb & AHB_LVL0INT) ? AHB_CLRLVL0INT : 0;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun if (val) {
270*4882a593Smuzhiyun iisahb |= val;
271*4882a593Smuzhiyun writel(iisahb, idma.regs + I2SAHB);
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun addr = readl(idma.regs + I2SLVL0ADDR) - idma.lp_tx_addr;
274*4882a593Smuzhiyun addr += prtd->periodsz;
275*4882a593Smuzhiyun addr %= (u32)(prtd->end - prtd->start);
276*4882a593Smuzhiyun addr += idma.lp_tx_addr;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun writel(addr, idma.regs + I2SLVL0ADDR);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun if (prtd->cb)
281*4882a593Smuzhiyun prtd->cb(prtd->token, prtd->period);
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun return IRQ_HANDLED;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
idma_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)287*4882a593Smuzhiyun static int idma_open(struct snd_soc_component *component,
288*4882a593Smuzhiyun struct snd_pcm_substream *substream)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
291*4882a593Smuzhiyun struct idma_ctrl *prtd;
292*4882a593Smuzhiyun int ret;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun snd_soc_set_runtime_hwparams(substream, &idma_hardware);
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun prtd = kzalloc(sizeof(struct idma_ctrl), GFP_KERNEL);
297*4882a593Smuzhiyun if (prtd == NULL)
298*4882a593Smuzhiyun return -ENOMEM;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun ret = request_irq(idma_irq, iis_irq, 0, "i2s", prtd);
301*4882a593Smuzhiyun if (ret < 0) {
302*4882a593Smuzhiyun pr_err("fail to claim i2s irq , ret = %d\n", ret);
303*4882a593Smuzhiyun kfree(prtd);
304*4882a593Smuzhiyun return ret;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun spin_lock_init(&prtd->lock);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun runtime->private_data = prtd;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun return 0;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
idma_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)314*4882a593Smuzhiyun static int idma_close(struct snd_soc_component *component,
315*4882a593Smuzhiyun struct snd_pcm_substream *substream)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
318*4882a593Smuzhiyun struct idma_ctrl *prtd = runtime->private_data;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun free_irq(idma_irq, prtd);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun if (!prtd)
323*4882a593Smuzhiyun pr_err("idma_close called with prtd == NULL\n");
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun kfree(prtd);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun return 0;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
idma_free(struct snd_soc_component * component,struct snd_pcm * pcm)330*4882a593Smuzhiyun static void idma_free(struct snd_soc_component *component,
331*4882a593Smuzhiyun struct snd_pcm *pcm)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun struct snd_pcm_substream *substream;
334*4882a593Smuzhiyun struct snd_dma_buffer *buf;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
337*4882a593Smuzhiyun if (!substream)
338*4882a593Smuzhiyun return;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun buf = &substream->dma_buffer;
341*4882a593Smuzhiyun if (!buf->area)
342*4882a593Smuzhiyun return;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun iounmap((void __iomem *)buf->area);
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun buf->area = NULL;
347*4882a593Smuzhiyun buf->addr = 0;
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun
preallocate_idma_buffer(struct snd_pcm * pcm,int stream)350*4882a593Smuzhiyun static int preallocate_idma_buffer(struct snd_pcm *pcm, int stream)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun struct snd_pcm_substream *substream = pcm->streams[stream].substream;
353*4882a593Smuzhiyun struct snd_dma_buffer *buf = &substream->dma_buffer;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun buf->dev.dev = pcm->card->dev;
356*4882a593Smuzhiyun buf->private_data = NULL;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun /* Assign PCM buffer pointers */
359*4882a593Smuzhiyun buf->dev.type = SNDRV_DMA_TYPE_CONTINUOUS;
360*4882a593Smuzhiyun buf->addr = idma.lp_tx_addr;
361*4882a593Smuzhiyun buf->bytes = idma_hardware.buffer_bytes_max;
362*4882a593Smuzhiyun buf->area = (unsigned char * __force)ioremap(buf->addr, buf->bytes);
363*4882a593Smuzhiyun if (!buf->area)
364*4882a593Smuzhiyun return -ENOMEM;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun return 0;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
idma_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)369*4882a593Smuzhiyun static int idma_new(struct snd_soc_component *component,
370*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun struct snd_card *card = rtd->card->snd_card;
373*4882a593Smuzhiyun struct snd_pcm *pcm = rtd->pcm;
374*4882a593Smuzhiyun int ret;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
377*4882a593Smuzhiyun if (ret)
378*4882a593Smuzhiyun return ret;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
381*4882a593Smuzhiyun ret = preallocate_idma_buffer(pcm,
382*4882a593Smuzhiyun SNDRV_PCM_STREAM_PLAYBACK);
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun return ret;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun
idma_reg_addr_init(void __iomem * regs,dma_addr_t addr)388*4882a593Smuzhiyun void idma_reg_addr_init(void __iomem *regs, dma_addr_t addr)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun spin_lock_init(&idma.lock);
391*4882a593Smuzhiyun idma.regs = regs;
392*4882a593Smuzhiyun idma.lp_tx_addr = addr;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(idma_reg_addr_init);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun static const struct snd_soc_component_driver asoc_idma_platform = {
397*4882a593Smuzhiyun .open = idma_open,
398*4882a593Smuzhiyun .close = idma_close,
399*4882a593Smuzhiyun .trigger = idma_trigger,
400*4882a593Smuzhiyun .pointer = idma_pointer,
401*4882a593Smuzhiyun .mmap = idma_mmap,
402*4882a593Smuzhiyun .hw_params = idma_hw_params,
403*4882a593Smuzhiyun .hw_free = idma_hw_free,
404*4882a593Smuzhiyun .prepare = idma_prepare,
405*4882a593Smuzhiyun .pcm_construct = idma_new,
406*4882a593Smuzhiyun .pcm_destruct = idma_free,
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun
asoc_idma_platform_probe(struct platform_device * pdev)409*4882a593Smuzhiyun static int asoc_idma_platform_probe(struct platform_device *pdev)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun idma_irq = platform_get_irq(pdev, 0);
412*4882a593Smuzhiyun if (idma_irq < 0)
413*4882a593Smuzhiyun return idma_irq;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun return devm_snd_soc_register_component(&pdev->dev, &asoc_idma_platform,
416*4882a593Smuzhiyun NULL, 0);
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun static struct platform_driver asoc_idma_driver = {
420*4882a593Smuzhiyun .driver = {
421*4882a593Smuzhiyun .name = "samsung-idma",
422*4882a593Smuzhiyun },
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun .probe = asoc_idma_platform_probe,
425*4882a593Smuzhiyun };
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun module_platform_driver(asoc_idma_driver);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
430*4882a593Smuzhiyun MODULE_DESCRIPTION("Samsung ASoC IDMA Driver");
431*4882a593Smuzhiyun MODULE_LICENSE("GPL");
432