xref: /OK3568_Linux_fs/kernel/sound/soc/samsung/i2s-regs.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4*4882a593Smuzhiyun  *		http://www.samsung.com
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Samsung I2S driver's register header
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #ifndef __SND_SOC_SAMSUNG_I2S_REGS_H
10*4882a593Smuzhiyun #define __SND_SOC_SAMSUNG_I2S_REGS_H
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define I2SCON		0x0
13*4882a593Smuzhiyun #define I2SMOD		0x4
14*4882a593Smuzhiyun #define I2SFIC		0x8
15*4882a593Smuzhiyun #define I2SPSR		0xc
16*4882a593Smuzhiyun #define I2STXD		0x10
17*4882a593Smuzhiyun #define I2SRXD		0x14
18*4882a593Smuzhiyun #define I2SFICS		0x18
19*4882a593Smuzhiyun #define I2STXDS		0x1c
20*4882a593Smuzhiyun #define I2SAHB		0x20
21*4882a593Smuzhiyun #define I2SSTR0		0x24
22*4882a593Smuzhiyun #define I2SSIZE		0x28
23*4882a593Smuzhiyun #define I2STRNCNT	0x2c
24*4882a593Smuzhiyun #define I2SLVL0ADDR	0x30
25*4882a593Smuzhiyun #define I2SLVL1ADDR	0x34
26*4882a593Smuzhiyun #define I2SLVL2ADDR	0x38
27*4882a593Smuzhiyun #define I2SLVL3ADDR	0x3c
28*4882a593Smuzhiyun #define I2SSTR1		0x40
29*4882a593Smuzhiyun #define I2SVER		0x44
30*4882a593Smuzhiyun #define I2SFIC1		0x48
31*4882a593Smuzhiyun #define I2STDM		0x4c
32*4882a593Smuzhiyun #define I2SFSTA		0x50
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define CON_RSTCLR		(1 << 31)
35*4882a593Smuzhiyun #define CON_FRXOFSTATUS		(1 << 26)
36*4882a593Smuzhiyun #define CON_FRXORINTEN		(1 << 25)
37*4882a593Smuzhiyun #define CON_FTXSURSTAT		(1 << 24)
38*4882a593Smuzhiyun #define CON_FTXSURINTEN		(1 << 23)
39*4882a593Smuzhiyun #define CON_TXSDMA_PAUSE	(1 << 20)
40*4882a593Smuzhiyun #define CON_TXSDMA_ACTIVE	(1 << 18)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define CON_FTXURSTATUS		(1 << 17)
43*4882a593Smuzhiyun #define CON_FTXURINTEN		(1 << 16)
44*4882a593Smuzhiyun #define CON_TXFIFO2_EMPTY	(1 << 15)
45*4882a593Smuzhiyun #define CON_TXFIFO1_EMPTY	(1 << 14)
46*4882a593Smuzhiyun #define CON_TXFIFO2_FULL	(1 << 13)
47*4882a593Smuzhiyun #define CON_TXFIFO1_FULL	(1 << 12)
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define CON_LRINDEX		(1 << 11)
50*4882a593Smuzhiyun #define CON_TXFIFO_EMPTY	(1 << 10)
51*4882a593Smuzhiyun #define CON_RXFIFO_EMPTY	(1 << 9)
52*4882a593Smuzhiyun #define CON_TXFIFO_FULL		(1 << 8)
53*4882a593Smuzhiyun #define CON_RXFIFO_FULL		(1 << 7)
54*4882a593Smuzhiyun #define CON_TXDMA_PAUSE		(1 << 6)
55*4882a593Smuzhiyun #define CON_RXDMA_PAUSE		(1 << 5)
56*4882a593Smuzhiyun #define CON_TXCH_PAUSE		(1 << 4)
57*4882a593Smuzhiyun #define CON_RXCH_PAUSE		(1 << 3)
58*4882a593Smuzhiyun #define CON_TXDMA_ACTIVE	(1 << 2)
59*4882a593Smuzhiyun #define CON_RXDMA_ACTIVE	(1 << 1)
60*4882a593Smuzhiyun #define CON_ACTIVE		(1 << 0)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define MOD_OPCLK_SHIFT		30
63*4882a593Smuzhiyun #define MOD_OPCLK_CDCLK_OUT	(0 << MOD_OPCLK_SHIFT)
64*4882a593Smuzhiyun #define MOD_OPCLK_CDCLK_IN	(1 << MOD_OPCLK_SHIFT)
65*4882a593Smuzhiyun #define MOD_OPCLK_BCLK_OUT	(2 << MOD_OPCLK_SHIFT)
66*4882a593Smuzhiyun #define MOD_OPCLK_PCLK		(3 << MOD_OPCLK_SHIFT)
67*4882a593Smuzhiyun #define MOD_OPCLK_MASK		(3 << MOD_OPCLK_SHIFT)
68*4882a593Smuzhiyun #define MOD_TXS_IDMA		(1 << 28) /* Sec_TXFIFO use I-DMA */
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define MOD_BLCS_SHIFT		26
71*4882a593Smuzhiyun #define MOD_BLCS_16BIT		(0 << MOD_BLCS_SHIFT)
72*4882a593Smuzhiyun #define MOD_BLCS_8BIT		(1 << MOD_BLCS_SHIFT)
73*4882a593Smuzhiyun #define MOD_BLCS_24BIT		(2 << MOD_BLCS_SHIFT)
74*4882a593Smuzhiyun #define MOD_BLCS_MASK		(3 << MOD_BLCS_SHIFT)
75*4882a593Smuzhiyun #define MOD_BLCP_SHIFT		24
76*4882a593Smuzhiyun #define MOD_BLCP_16BIT		(0 << MOD_BLCP_SHIFT)
77*4882a593Smuzhiyun #define MOD_BLCP_8BIT		(1 << MOD_BLCP_SHIFT)
78*4882a593Smuzhiyun #define MOD_BLCP_24BIT		(2 << MOD_BLCP_SHIFT)
79*4882a593Smuzhiyun #define MOD_BLCP_MASK		(3 << MOD_BLCP_SHIFT)
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define MOD_C2DD_HHALF		(1 << 21) /* Discard Higher-half */
82*4882a593Smuzhiyun #define MOD_C2DD_LHALF		(1 << 20) /* Discard Lower-half */
83*4882a593Smuzhiyun #define MOD_C1DD_HHALF		(1 << 19)
84*4882a593Smuzhiyun #define MOD_C1DD_LHALF		(1 << 18)
85*4882a593Smuzhiyun #define MOD_DC2_EN		(1 << 17)
86*4882a593Smuzhiyun #define MOD_DC1_EN		(1 << 16)
87*4882a593Smuzhiyun #define MOD_BLC_16BIT		(0 << 13)
88*4882a593Smuzhiyun #define MOD_BLC_8BIT		(1 << 13)
89*4882a593Smuzhiyun #define MOD_BLC_24BIT		(2 << 13)
90*4882a593Smuzhiyun #define MOD_BLC_MASK		(3 << 13)
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define MOD_TXONLY		(0 << 8)
93*4882a593Smuzhiyun #define MOD_RXONLY		(1 << 8)
94*4882a593Smuzhiyun #define MOD_TXRX		(2 << 8)
95*4882a593Smuzhiyun #define MOD_MASK		(3 << 8)
96*4882a593Smuzhiyun #define MOD_LRP_SHIFT		7
97*4882a593Smuzhiyun #define MOD_LR_LLOW		0
98*4882a593Smuzhiyun #define MOD_LR_RLOW		1
99*4882a593Smuzhiyun #define MOD_SDF_SHIFT		5
100*4882a593Smuzhiyun #define MOD_SDF_IIS		0
101*4882a593Smuzhiyun #define MOD_SDF_MSB		1
102*4882a593Smuzhiyun #define MOD_SDF_LSB		2
103*4882a593Smuzhiyun #define MOD_SDF_MASK		3
104*4882a593Smuzhiyun #define MOD_RCLK_SHIFT		3
105*4882a593Smuzhiyun #define MOD_RCLK_256FS		0
106*4882a593Smuzhiyun #define MOD_RCLK_512FS		1
107*4882a593Smuzhiyun #define MOD_RCLK_384FS		2
108*4882a593Smuzhiyun #define MOD_RCLK_768FS		3
109*4882a593Smuzhiyun #define MOD_RCLK_MASK		3
110*4882a593Smuzhiyun #define MOD_BCLK_SHIFT		1
111*4882a593Smuzhiyun #define MOD_BCLK_32FS		0
112*4882a593Smuzhiyun #define MOD_BCLK_48FS		1
113*4882a593Smuzhiyun #define MOD_BCLK_16FS		2
114*4882a593Smuzhiyun #define MOD_BCLK_24FS		3
115*4882a593Smuzhiyun #define MOD_BCLK_MASK		3
116*4882a593Smuzhiyun #define MOD_8BIT		(1 << 0)
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #define EXYNOS5420_MOD_LRP_SHIFT	15
119*4882a593Smuzhiyun #define EXYNOS5420_MOD_SDF_SHIFT	6
120*4882a593Smuzhiyun #define EXYNOS5420_MOD_RCLK_SHIFT	4
121*4882a593Smuzhiyun #define EXYNOS5420_MOD_BCLK_SHIFT	0
122*4882a593Smuzhiyun #define EXYNOS5420_MOD_BCLK_64FS	4
123*4882a593Smuzhiyun #define EXYNOS5420_MOD_BCLK_96FS	5
124*4882a593Smuzhiyun #define EXYNOS5420_MOD_BCLK_128FS	6
125*4882a593Smuzhiyun #define EXYNOS5420_MOD_BCLK_192FS	7
126*4882a593Smuzhiyun #define EXYNOS5420_MOD_BCLK_256FS	8
127*4882a593Smuzhiyun #define EXYNOS5420_MOD_BCLK_MASK	0xf
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #define EXYNOS7_MOD_RCLK_64FS	4
130*4882a593Smuzhiyun #define EXYNOS7_MOD_RCLK_128FS	5
131*4882a593Smuzhiyun #define EXYNOS7_MOD_RCLK_96FS	6
132*4882a593Smuzhiyun #define EXYNOS7_MOD_RCLK_192FS	7
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun #define PSR_PSREN		(1 << 15)
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun #define FIC_TX2COUNT(x)		(((x) >>  24) & 0xf)
137*4882a593Smuzhiyun #define FIC_TX1COUNT(x)		(((x) >>  16) & 0xf)
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun #define FIC_TXFLUSH		(1 << 15)
140*4882a593Smuzhiyun #define FIC_RXFLUSH		(1 << 7)
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun #define FIC_TXCOUNT(x)		(((x) >>  8) & 0xf)
143*4882a593Smuzhiyun #define FIC_RXCOUNT(x)		(((x) >>  0) & 0xf)
144*4882a593Smuzhiyun #define FICS_TXCOUNT(x)		(((x) >>  8) & 0x7f)
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun #define AHB_INTENLVL0		(1 << 24)
147*4882a593Smuzhiyun #define AHB_LVL0INT		(1 << 20)
148*4882a593Smuzhiyun #define AHB_CLRLVL0INT		(1 << 16)
149*4882a593Smuzhiyun #define AHB_DMARLD		(1 << 5)
150*4882a593Smuzhiyun #define AHB_INTMASK		(1 << 3)
151*4882a593Smuzhiyun #define AHB_DMAEN		(1 << 0)
152*4882a593Smuzhiyun #define AHB_LVLINTMASK		(0xf << 20)
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun #define I2SSIZE_TRNMSK		(0xffff)
155*4882a593Smuzhiyun #define I2SSIZE_SHIFT		(16)
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun #endif /* __SND_SOC_SAMSUNG_I2S_REGS_H */
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