1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Rockchip VAD Preprocess 4 * 5 * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd 6 * 7 */ 8 9 .syntax unified 10 .arch armv7-a 11 .fpu softvfp 12 .eabi_attribute 20, 1 13 .eabi_attribute 21, 1 14 .eabi_attribute 23, 3 15 .eabi_attribute 24, 1 16 .eabi_attribute 25, 1 17 .eabi_attribute 26, 2 18 .eabi_attribute 30, 4 19 .eabi_attribute 34, 1 20 .eabi_attribute 18, 4 21 .thumb 22 .file "vad_preprocess_thumb.S" 23 .text 24 .align 1 25 .global vad_preprocess_init 26 .thumb 27 .thumb_func 28 .type vad_preprocess_init, %function 29vad_preprocess_init: 30 .fnstart 31 @ args = 0, pretend = 0, frame = 0 32 @ frame_needed = 0, uses_anonymous_args = 0 33 @ link register save eliminated. 34 ldr r2, .L4 35 ldr r3, [r0, #8] 36 strh r3, [r2] @ movhi 37 ldr r3, [r0, #4] 38 strh r3, [r2, #2] @ movhi 39 ldr r3, [r0, #12] 40 strh r3, [r2, #4] @ movhi 41 ldr r3, [r0] 42 strh r3, [r2, #6] @ movhi 43 ldr r3, [r0, #16] 44 tst r3, #512 45 ubfx r3, r3, #0, #9 46 itte ne 47 eorne r3, r3, #65280 48 eorne r3, r3, #255 49 uxtheq r3, r3 50 strh r3, [r2, #8] @ movhi 51 bx lr 52.L5: 53 .align 2 54.L4: 55 .word .LANCHOR0 56 .fnend 57 .size vad_preprocess_init, .-vad_preprocess_init 58 .align 1 59 .global vad_preprocess 60 .thumb 61 .thumb_func 62 .type vad_preprocess, %function 63vad_preprocess: 64 .fnstart 65 @ args = 0, pretend = 0, frame = 0 66 @ frame_needed = 0, uses_anonymous_args = 0 67 ldr r3, .L29 68 movw r2, #34839 69 push {r4, r5, r6, r7, r8, r9, lr} 70 .save {r4, r5, r6, r7, r8, r9, lr} 71 movw r1, #15349 72 ldrsh r5, [r3, #8] 73 muls r0, r5, r0 74 ldrh r7, [r3, #10] 75 it mi 76 addmi r0, r0, #31 77 ldrh r4, [r3, #12] 78 asrs r0, r0, #5 79 ldrh r6, [r3, #14] 80 smulbb r2, r7, r2 81 mla r2, r1, r0, r2 82 smlabb r2, r4, r1, r2 83 movw r1, #34904 84 smulbb r1, r6, r1 85 ldrsh r4, [r3, #16] 86 subs r1, r2, r1 87 movw r2, #14379 88 mls r4, r4, r2, r1 89 cmp r4, #1 90 asr r5, r4, #31 91 sbcs r2, r5, #0 92 blt .L8 93 adds r4, r4, #8192 94 adc r5, r5, #0 95 b .L10 96.L8: 97 subs r4, r4, #8192 98 adc r5, r5, #-1 99 cmp r4, #0 100 sbcs r2, r5, #0 101 bge .L10 102 movw r8, #16383 103 mov r9, #0 104 adds r4, r4, r8 105 adc r5, r5, r9 106.L10: 107 lsrs r1, r4, #14 108 ldrh r4, [r3, #18] 109 orr r1, r1, r5, lsl #18 110 ldr r2, .L29+4 111 adds r4, r4, #1 112 strh r0, [r3, #10] @ movhi 113 uxth r1, r1 114 strh r1, [r3, #14] @ movhi 115 uxth r4, r4 116 strh r4, [r3, #18] @ movhi 117 sxth r1, r1 118 ldr r0, [r3, #20] 119 sxth r4, r4 120 cmp r1, #0 121 and r2, r2, r4 122 it lt 123 rsblt r1, r1, #0 124 cmp r2, #0 125 add r0, r0, r1 126 it lt 127 addlt r2, r2, #-1 128 strh r7, [r3, #12] @ movhi 129 it lt 130 ornlt r2, r2, #255 131 strh r6, [r3, #16] @ movhi 132 it lt 133 addlt r2, r2, #1 134 str r0, [r3, #20] 135 cmp r2, #0 136 bne .L11 137 ldr r4, [r3, #24] 138 ldr r2, .L29 139 cmp r4, #99 140 bgt .L13 141 adds r5, r0, #128 142 add r2, r2, r4, lsl #1 143 it mi 144 addwmi r5, r0, #383 145 asrs r5, r5, #8 146 strh r5, [r2, #28] @ movhi 147 b .L15 148.L13: 149 add r5, r2, #28 150 adds r2, r2, #226 151.L16: 152 ldrh r6, [r5, #2] 153 strh r6, [r5], #2 @ movhi 154 cmp r5, r2 155 bne .L16 156 adds r2, r0, #128 157 it mi 158 addwmi r2, r0, #383 159 ldr r0, .L29 160 asrs r2, r2, #8 161 strh r2, [r0, #226] @ movhi 162.L15: 163 cmp r4, #99 164 ldrh r2, [r3, #28] 165 mov r0, #1 166 bgt .L18 167 ldr r5, .L29+8 168.L19: 169 cmp r0, r4 170 bge .L21 171 ldrsh r6, [r5, r0, lsl #1] 172 sxth r2, r2 173 adds r0, r0, #1 174 cmp r2, r6 175 it ge 176 movge r2, r6 177 uxth r2, r2 178 b .L19 179.L18: 180 ldr r6, .L29+8 181.L22: 182 ldrsh r5, [r6, r0, lsl #1] 183 sxth r2, r2 184 adds r0, r0, #1 185 cmp r2, r5 186 it ge 187 movge r2, r5 188 cmp r0, #100 189 uxth r2, r2 190 bne .L22 191.L21: 192 ldrh r5, [r3, #6] 193 movs r0, #128 194 movs r6, #230 195 adds r4, r4, #1 196 str r4, [r3, #24] 197 smlabb r0, r5, r6, r0 198 movs r5, #26 199 smlabb r2, r2, r5, r0 200 ldr r0, .L29 201 cmp r2, #0 202 it lt 203 addlt r2, r2, #255 204 asrs r2, r2, #8 205 strh r2, [r0, #6] @ movhi 206 movs r2, #0 207 str r2, [r3, #20] 208 strh r2, [r3, #18] @ movhi 209.L11: 210 ldrh r0, [r3, #6] 211 ldrh r4, [r3, #2] 212 ldrsh r3, [r3] 213 ldr r2, .L29 214 smlabb r3, r0, r4, r3 215 cmp r1, r3 216 ble .L24 217 ldrh r3, [r2, #428] 218 ldrsh r0, [r2, #4] 219 adds r3, r3, #1 220 uxth r3, r3 221 strh r3, [r2, #428] @ movhi 222 sxth r3, r3 223 cmp r0, r3 224 ite ge 225 movge r0, #0 226 movlt r0, #1 227 pop {r4, r5, r6, r7, r8, r9, pc} 228.L24: 229 movs r0, #0 230 strh r0, [r2, #428] @ movhi 231 pop {r4, r5, r6, r7, r8, r9, pc} 232.L30: 233 .align 2 234.L29: 235 .word .LANCHOR0 236 .word -2147483393 237 .word .LANCHOR0+28 238 .fnend 239 .size vad_preprocess, .-vad_preprocess 240 .align 1 241 .global vad_preprocess_destroy 242 .thumb 243 .thumb_func 244 .type vad_preprocess_destroy, %function 245vad_preprocess_destroy: 246 .fnstart 247 @ args = 0, pretend = 0, frame = 0 248 @ frame_needed = 0, uses_anonymous_args = 0 249 movs r3, #0 250 ldr r2, .L34 251 push {r4, lr} 252 .save {r4, lr} 253 mov r4, r3 254 strh r3, [r2, #10] @ movhi 255 strh r3, [r2, #12] @ movhi 256 strh r3, [r2, #14] @ movhi 257 strh r3, [r2, #16] @ movhi 258 strh r3, [r2, #18] @ movhi 259 strh r3, [r2, #428] @ movhi 260.L32: 261 ldr r2, .L34 262 movs r1, #0 263 add r0, r2, #28 264 strh r4, [r0, r3, lsl #1] @ movhi 265 adds r3, r3, #1 266 cmp r3, #100 267 bne .L32 268 movs r3, #32 269 str r1, [r2, #20] 270 strh r1, [r2, #6] @ movhi 271 strh r3, [r2, #8] @ movhi 272 str r1, [r2, #24] 273 pop {r4, pc} 274.L35: 275 .align 2 276.L34: 277 .word .LANCHOR0 278 .fnend 279 .size vad_preprocess_destroy, .-vad_preprocess_destroy 280 .align 1 281 .global vad_preprocess_update_params 282 .thumb 283 .thumb_func 284 .type vad_preprocess_update_params, %function 285vad_preprocess_update_params: 286 .fnstart 287 @ args = 0, pretend = 0, frame = 0 288 @ frame_needed = 0, uses_anonymous_args = 0 289 @ link register save eliminated. 290 ldr r3, .L37 291 ldrsh r3, [r3, #6] 292 str r3, [r0] 293 bx lr 294.L38: 295 .align 2 296.L37: 297 .word .LANCHOR0 298 .fnend 299 .size vad_preprocess_update_params, .-vad_preprocess_update_params 300 .bss 301 .align 2 302.LANCHOR0 = . + 0 303 .type g_sound_thd, %object 304 .size g_sound_thd, 2 305g_sound_thd: 306 .space 2 307 .type g_noise_level, %object 308 .size g_noise_level, 2 309g_noise_level: 310 .space 2 311 .type g_vad_con_thd, %object 312 .size g_vad_con_thd, 2 313g_vad_con_thd: 314 .space 2 315 .type g_noise_abs, %object 316 .size g_noise_abs, 2 317g_noise_abs: 318 .space 2 319 .type g_signal_gain, %object 320 .size g_signal_gain, 2 321g_signal_gain: 322 .space 2 323 .type g_xn_1, %object 324 .size g_xn_1, 2 325g_xn_1: 326 .space 2 327 .type g_xn_2, %object 328 .size g_xn_2, 2 329g_xn_2: 330 .space 2 331 .type g_yn_1, %object 332 .size g_yn_1, 2 333g_yn_1: 334 .space 2 335 .type g_yn_2, %object 336 .size g_yn_2, 2 337g_yn_2: 338 .space 2 339 .type g_sample_cnt, %object 340 .size g_sample_cnt, 2 341g_sample_cnt: 342 .space 2 343 .type g_sum_abs_frm, %object 344 .size g_sum_abs_frm, 4 345g_sum_abs_frm: 346 .space 4 347 .type frm_count, %object 348 .size frm_count, 4 349frm_count: 350 .space 4 351 .type g_ave_abs_rec, %object 352 .size g_ave_abs_rec, 400 353g_ave_abs_rec: 354 .space 400 355 .type g_vad_cnt, %object 356 .size g_vad_cnt, 2 357g_vad_cnt: 358 .space 2 359 .ident "GCC: (GNU) 4.9 20150123 (prerelease)" 360 .section .note.GNU-stack,"",%progbits 361