xref: /OK3568_Linux_fs/kernel/sound/soc/rockchip/rockchip_spdifrx.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * ALSA SoC Audio Layer - Rockchip SPDIF_RX Controller driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #ifndef _ROCKCHIP_SPDIFRX_H
10*4882a593Smuzhiyun #define _ROCKCHIP_SPDIFRX_H
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun /* CFGR */
13*4882a593Smuzhiyun #define SPDIFRX_CFGR_TWAD_SHIFT		1
14*4882a593Smuzhiyun #define SPDIFRX_CFGR_TWAD_DATA_ONLY	(0 << 1)
15*4882a593Smuzhiyun #define SPDIFRX_CFGR_TWAD_STREAM	BIT(1)
16*4882a593Smuzhiyun #define SPDIFRX_EN_MASK			BIT(0)
17*4882a593Smuzhiyun #define SPDIFRX_EN			BIT(0)
18*4882a593Smuzhiyun #define SPDIFRX_DIS			0
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /* CLR */
21*4882a593Smuzhiyun #define SPDIFRX_CLR_RXSC		BIT(0)
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun /* CDR */
24*4882a593Smuzhiyun #define SPDIFRX_CDR_CS_MASK		GENMASK(10, 9)
25*4882a593Smuzhiyun #define SPDIFRX_CDR_AVGSEL_MASK		BIT(1)
26*4882a593Smuzhiyun #define SPDIFRX_CDR_AVGSEL_MIN		(0 << 1)
27*4882a593Smuzhiyun #define SPDIFRX_CDR_AVGSEL_AVG		BIT(1)
28*4882a593Smuzhiyun #define SPDIFRX_CDR_BYPASS_MASK		BIT(0)
29*4882a593Smuzhiyun #define SPDIFRX_CDR_BYPASS_EN		BIT(0)
30*4882a593Smuzhiyun #define SPDIFRX_CDR_BYPASS_DIS		0
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* CDRST */
33*4882a593Smuzhiyun #define SPDIFRX_CDRST_NOSTRTHR_MASK	GENMASK(31, 16)
34*4882a593Smuzhiyun #define SPDIFRX_CDRST_MAXCNT_MASK	GENMASK(15, 8)
35*4882a593Smuzhiyun #define SPDIFRX_CDRST_MINCNT_MASK	GENMASK(7, 0)
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* DMACR */
38*4882a593Smuzhiyun #define SPDIFRX_DMACR_RDE_MASK		BIT(5)
39*4882a593Smuzhiyun #define SPDIFRX_DMACR_RDE_DISABLE	(0 << 5)
40*4882a593Smuzhiyun #define SPDIFRX_DMACR_RDE_ENABLE	BIT(5)
41*4882a593Smuzhiyun #define SPDIFRX_DMACR_RDL_MASK		GENMASK(4, 0)
42*4882a593Smuzhiyun #define SPDIFRX_DMACR_RDL(x)		(((x) - 1) << 0)
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun /* FIFOCTRL */
45*4882a593Smuzhiyun #define SPDIFRX_FIFOCTRL_RFL_MASK	GENMASK(13, 8)
46*4882a593Smuzhiyun #define SPDIFRX_FIFOCTRL_RFT_MASK	GENMASK(4, 0)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* INTEN */
49*4882a593Smuzhiyun #define SPDIFRX_INTEN_UBCIE_MASK	BIT(10)
50*4882a593Smuzhiyun #define SPDIFRX_INTEN_UBCIE_EN		BIT(10)
51*4882a593Smuzhiyun #define SPDIFRX_INTEN_UBCIE_DIS		(0 << 10)
52*4882a593Smuzhiyun #define SPDIFRX_INTEN_SYNCIE_MASK	BIT(9)
53*4882a593Smuzhiyun #define SPDIFRX_INTEN_SYNCIE_EN		BIT(9)
54*4882a593Smuzhiyun #define SPDIFRX_INTEN_SYNCIE_DIS	(0 << 9)
55*4882a593Smuzhiyun #define SPDIFRX_INTEN_BTEIE_MASK	BIT(8)
56*4882a593Smuzhiyun #define SPDIFRX_INTEN_BTEIE_EN		BIT(8)
57*4882a593Smuzhiyun #define SPDIFRX_INTEN_BTEIE_DIS		(0 << 8)
58*4882a593Smuzhiyun #define SPDIFRX_INTEN_NSYNCIE_MASK	BIT(7)
59*4882a593Smuzhiyun #define SPDIFRX_INTEN_NSYNCIE_EN	BIT(7)
60*4882a593Smuzhiyun #define SPDIFRX_INTEN_NSYNCIE_DIS	(0 << 7)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* INTMASK */
63*4882a593Smuzhiyun #define SPDIFRX_INTMASK_UBCIMSK		BIT(10)
64*4882a593Smuzhiyun #define SPDIFRX_INTMASK_UBCIUMSK	(0 << 10)
65*4882a593Smuzhiyun #define SPDIFRX_INTMASK_SYNCIMSK	BIT(9)
66*4882a593Smuzhiyun #define SPDIFRX_INTMASK_SYNCIUMSK	(0 << 9)
67*4882a593Smuzhiyun #define SPDIFRX_INTMASK_BTEIMSK		BIT(8)
68*4882a593Smuzhiyun #define SPDIFRX_INTMASK_BTEIUMSK	(0 << 8)
69*4882a593Smuzhiyun #define SPDIFRX_INTMASK_NSYNCIMSK	BIT(7)
70*4882a593Smuzhiyun #define SPDIFRX_INTMASK_NSYNCIUMSK	(0 << 7)
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* INTSR */
73*4882a593Smuzhiyun #define SPDIFRX_INTSR_UBCISR_ACTIVE	BIT(10)
74*4882a593Smuzhiyun #define SPDIFRX_INTSR_SYNCISR_ACTIVE	BIT(9)
75*4882a593Smuzhiyun #define SPDIFRX_INTSR_BTEISR_ACTIVE	BIT(8)
76*4882a593Smuzhiyun #define SPDIFRX_INTSR_NSYNCISR_ACTIVE	BIT(7)
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /* INTCLR */
79*4882a593Smuzhiyun #define SPDIFRX_INTCLR_UBCICLR_MASK	BIT(10)
80*4882a593Smuzhiyun #define SPDIFRX_INTCLR_UBCICLR		BIT(10)
81*4882a593Smuzhiyun #define SPDIFRX_INTCLR_SYNCICLR_MASK	BIT(9)
82*4882a593Smuzhiyun #define SPDIFRX_INTCLR_SYNCICLR		BIT(9)
83*4882a593Smuzhiyun #define SPDIFRX_INTCLR_BTECLR_MASK	BIT(8)
84*4882a593Smuzhiyun #define SPDIFRX_INTCLR_BIECLR		BIT(8)
85*4882a593Smuzhiyun #define SPDIFRX_INTCLR_NSYNCICLR_MASK	BIT(7)
86*4882a593Smuzhiyun #define SPDIFRX_INTCLR_NSYNCICLR	BIT(7)
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /* BURSTINFO */
89*4882a593Smuzhiyun #define SPDIFRX_BURSTINFO_PD_MASK	GENMASK(31, 16)
90*4882a593Smuzhiyun #define SPDIFRX_BURSTINFO_BSNUM_MASK	GENMASK(15, 13)
91*4882a593Smuzhiyun #define SPDIFRX_BURSTINFO_DATAINFO_MASK	GENMASK(12, 8)
92*4882a593Smuzhiyun #define SPDIFRX_BURSTINFO_ERRFLAG_MASK	BIT(7)
93*4882a593Smuzhiyun #define SPDIFRX_BURSTINFO_ERR		BIT(7)
94*4882a593Smuzhiyun #define SPDIFRX_BURSTINFO_VALID		(0 << 7)
95*4882a593Smuzhiyun #define SPDIFRX_BURSTINFO_DATATYPE_MASK	GENMASK(6, 0)
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun #define SPDIFRX_VERSION			(0x0000)
98*4882a593Smuzhiyun #define SPDIFRX_CFGR			(0x0004)
99*4882a593Smuzhiyun #define SPDIFRX_CLR			(0x0008)
100*4882a593Smuzhiyun #define SPDIFRX_CDR			(0x000c)
101*4882a593Smuzhiyun #define SPDIFRX_CDRST			(0x0010)
102*4882a593Smuzhiyun #define SPDIFRX_DMACR			(0x0014)
103*4882a593Smuzhiyun #define SPDIFRX_FIFOCTRL		(0x0018)
104*4882a593Smuzhiyun #define SPDIFRX_INTEN			(0x001C)
105*4882a593Smuzhiyun #define SPDIFRX_INTMASK			(0x0020)
106*4882a593Smuzhiyun #define SPDIFRX_INTSR			(0x0024)
107*4882a593Smuzhiyun #define SPDIFRX_INTCLR			(0x0028)
108*4882a593Smuzhiyun #define SPDIFRX_SMPDR			(0x002C)
109*4882a593Smuzhiyun #define SPDIFRX_USRDRN			(0x0030)
110*4882a593Smuzhiyun #define SPDIFRX_CHNSRN			(0x0060)
111*4882a593Smuzhiyun #define SPDIFRX_BURSTINFO		(0x0100)
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun #endif /* _ROCKCHIP_SPDIFRX_H */
114