1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ALSA SoC Audio Layer - Rockchip SPDIF_RX Controller driver
4 *
5 * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd
6 *
7 */
8
9 #include <linux/module.h>
10 #include <linux/delay.h>
11 #include <linux/of_gpio.h>
12 #include <linux/clk.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17 #include <sound/pcm_params.h>
18 #include <sound/dmaengine_pcm.h>
19
20 #include "rockchip_spdifrx.h"
21
22 struct rk_spdifrx_dev {
23 struct device *dev;
24 struct clk *mclk;
25 struct clk *hclk;
26 struct snd_dmaengine_dai_dma_data capture_dma_data;
27 struct regmap *regmap;
28 struct reset_control *reset;
29 int irq;
30 };
31
rk_spdifrx_runtime_suspend(struct device * dev)32 static int rk_spdifrx_runtime_suspend(struct device *dev)
33 {
34 struct rk_spdifrx_dev *spdifrx = dev_get_drvdata(dev);
35
36 clk_disable_unprepare(spdifrx->mclk);
37 clk_disable_unprepare(spdifrx->hclk);
38
39 return 0;
40 }
41
rk_spdifrx_runtime_resume(struct device * dev)42 static int rk_spdifrx_runtime_resume(struct device *dev)
43 {
44 struct rk_spdifrx_dev *spdifrx = dev_get_drvdata(dev);
45 int ret;
46
47 ret = clk_prepare_enable(spdifrx->mclk);
48 if (ret) {
49 dev_err(spdifrx->dev, "mclk clock enable failed %d\n", ret);
50 return ret;
51 }
52
53 ret = clk_prepare_enable(spdifrx->hclk);
54 if (ret) {
55 dev_err(spdifrx->dev, "hclk clock enable failed %d\n", ret);
56 return ret;
57 }
58
59 return 0;
60 }
61
rk_spdifrx_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)62 static int rk_spdifrx_hw_params(struct snd_pcm_substream *substream,
63 struct snd_pcm_hw_params *params,
64 struct snd_soc_dai *dai)
65 {
66 struct rk_spdifrx_dev *spdifrx = snd_soc_dai_get_drvdata(dai);
67
68 regmap_update_bits(spdifrx->regmap, SPDIFRX_INTEN,
69 SPDIFRX_INTEN_SYNCIE_MASK |
70 SPDIFRX_INTEN_NSYNCIE_MASK,
71 SPDIFRX_INTEN_SYNCIE_EN |
72 SPDIFRX_INTEN_NSYNCIE_EN);
73 regmap_update_bits(spdifrx->regmap, SPDIFRX_DMACR,
74 SPDIFRX_DMACR_RDL_MASK, SPDIFRX_DMACR_RDL(8));
75 regmap_update_bits(spdifrx->regmap, SPDIFRX_CDR,
76 SPDIFRX_CDR_AVGSEL_MASK | SPDIFRX_CDR_BYPASS_MASK,
77 SPDIFRX_CDR_AVGSEL_MIN | SPDIFRX_CDR_BYPASS_DIS);
78 return 0;
79 }
80
rk_spdifrx_reset(struct rk_spdifrx_dev * spdifrx)81 static void rk_spdifrx_reset(struct rk_spdifrx_dev *spdifrx)
82 {
83 reset_control_assert(spdifrx->reset);
84 udelay(1);
85 reset_control_deassert(spdifrx->reset);
86 }
87
rk_spdifrx_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)88 static int rk_spdifrx_trigger(struct snd_pcm_substream *substream,
89 int cmd, struct snd_soc_dai *dai)
90 {
91 struct rk_spdifrx_dev *spdifrx = snd_soc_dai_get_drvdata(dai);
92 int ret;
93
94 switch (cmd) {
95 case SNDRV_PCM_TRIGGER_START:
96 case SNDRV_PCM_TRIGGER_RESUME:
97 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
98 rk_spdifrx_reset(spdifrx);
99 ret = regmap_update_bits(spdifrx->regmap, SPDIFRX_DMACR,
100 SPDIFRX_DMACR_RDE_MASK,
101 SPDIFRX_DMACR_RDE_ENABLE);
102
103 if (ret != 0)
104 return ret;
105
106 ret = regmap_update_bits(spdifrx->regmap, SPDIFRX_CFGR,
107 SPDIFRX_EN_MASK,
108 SPDIFRX_EN);
109 break;
110 case SNDRV_PCM_TRIGGER_SUSPEND:
111 case SNDRV_PCM_TRIGGER_STOP:
112 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
113 ret = regmap_update_bits(spdifrx->regmap, SPDIFRX_DMACR,
114 SPDIFRX_DMACR_RDE_MASK,
115 SPDIFRX_DMACR_RDE_DISABLE);
116
117 if (ret != 0)
118 return ret;
119
120 ret = regmap_update_bits(spdifrx->regmap, SPDIFRX_CFGR,
121 SPDIFRX_EN_MASK,
122 SPDIFRX_DIS);
123 break;
124 default:
125 ret = -EINVAL;
126 break;
127 }
128
129 return ret;
130 }
131
rk_spdifrx_dai_probe(struct snd_soc_dai * dai)132 static int rk_spdifrx_dai_probe(struct snd_soc_dai *dai)
133 {
134 struct rk_spdifrx_dev *spdifrx = snd_soc_dai_get_drvdata(dai);
135
136 dai->capture_dma_data = &spdifrx->capture_dma_data;
137
138 return 0;
139 }
140
141 static const struct snd_soc_dai_ops rk_spdifrx_dai_ops = {
142 .hw_params = rk_spdifrx_hw_params,
143 .trigger = rk_spdifrx_trigger,
144 };
145
146 static struct snd_soc_dai_driver rk_spdifrx_dai = {
147 .probe = rk_spdifrx_dai_probe,
148 .capture = {
149 .stream_name = "Capture",
150 .channels_min = 2,
151 .channels_max = 2,
152 .rates = (SNDRV_PCM_RATE_32000 |
153 SNDRV_PCM_RATE_44100 |
154 SNDRV_PCM_RATE_48000 |
155 SNDRV_PCM_RATE_96000 |
156 SNDRV_PCM_RATE_192000),
157 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
158 SNDRV_PCM_FMTBIT_S20_3LE |
159 SNDRV_PCM_FMTBIT_S24_LE),
160 },
161 .ops = &rk_spdifrx_dai_ops,
162 };
163
164 static const struct snd_soc_component_driver rk_spdifrx_component = {
165 .name = "rockchip-spdifrx",
166 };
167
rk_spdifrx_wr_reg(struct device * dev,unsigned int reg)168 static bool rk_spdifrx_wr_reg(struct device *dev, unsigned int reg)
169 {
170 switch (reg) {
171 case SPDIFRX_CFGR:
172 case SPDIFRX_CLR:
173 case SPDIFRX_CDR:
174 case SPDIFRX_CDRST:
175 case SPDIFRX_DMACR:
176 case SPDIFRX_FIFOCTRL:
177 case SPDIFRX_INTEN:
178 case SPDIFRX_INTMASK:
179 case SPDIFRX_INTSR:
180 case SPDIFRX_INTCLR:
181 case SPDIFRX_SMPDR:
182 case SPDIFRX_BURSTINFO:
183 return true;
184 default:
185 return false;
186 }
187 }
188
rk_spdifrx_rd_reg(struct device * dev,unsigned int reg)189 static bool rk_spdifrx_rd_reg(struct device *dev, unsigned int reg)
190 {
191 switch (reg) {
192 case SPDIFRX_CFGR:
193 case SPDIFRX_CLR:
194 case SPDIFRX_CDR:
195 case SPDIFRX_CDRST:
196 case SPDIFRX_DMACR:
197 case SPDIFRX_FIFOCTRL:
198 case SPDIFRX_INTEN:
199 case SPDIFRX_INTMASK:
200 case SPDIFRX_INTSR:
201 case SPDIFRX_INTCLR:
202 case SPDIFRX_SMPDR:
203 case SPDIFRX_BURSTINFO:
204 return true;
205 default:
206 return false;
207 }
208 }
209
rk_spdifrx_volatile_reg(struct device * dev,unsigned int reg)210 static bool rk_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
211 {
212 switch (reg) {
213 case SPDIFRX_CLR:
214 case SPDIFRX_CDR:
215 case SPDIFRX_CDRST:
216 case SPDIFRX_FIFOCTRL:
217 case SPDIFRX_INTSR:
218 case SPDIFRX_INTCLR:
219 case SPDIFRX_SMPDR:
220 case SPDIFRX_BURSTINFO:
221 return true;
222 default:
223 return false;
224 }
225 }
226
rk_spdifrx_precious_reg(struct device * dev,unsigned int reg)227 static bool rk_spdifrx_precious_reg(struct device *dev, unsigned int reg)
228 {
229 switch (reg) {
230 case SPDIFRX_SMPDR:
231 return true;
232 default:
233 return false;
234 }
235 }
236
237 static const struct regmap_config rk_spdifrx_regmap_config = {
238 .reg_bits = 32,
239 .reg_stride = 4,
240 .val_bits = 32,
241 .max_register = SPDIFRX_BURSTINFO,
242 .writeable_reg = rk_spdifrx_wr_reg,
243 .readable_reg = rk_spdifrx_rd_reg,
244 .volatile_reg = rk_spdifrx_volatile_reg,
245 .precious_reg = rk_spdifrx_precious_reg,
246 .cache_type = REGCACHE_FLAT,
247 };
248
rk_spdifrx_isr(int irq,void * dev_id)249 static irqreturn_t rk_spdifrx_isr(int irq, void *dev_id)
250 {
251 struct rk_spdifrx_dev *spdifrx = dev_id;
252 u32 intsr;
253
254 regmap_read(spdifrx->regmap, SPDIFRX_INTSR, &intsr);
255
256 if (intsr & BIT(7)) {
257 dev_dbg(spdifrx->dev, "NSYNC\n");
258 regmap_write(spdifrx->regmap, SPDIFRX_INTCLR, BIT(7));
259 }
260
261 if (intsr & BIT(9)) {
262 dev_dbg(spdifrx->dev, "SYNC\n");
263 regmap_write(spdifrx->regmap, SPDIFRX_INTCLR, BIT(9));
264 }
265
266 return IRQ_HANDLED;
267 }
268
rk_spdifrx_probe(struct platform_device * pdev)269 static int rk_spdifrx_probe(struct platform_device *pdev)
270 {
271 struct rk_spdifrx_dev *spdifrx;
272 struct resource *res;
273 void __iomem *regs;
274 int ret;
275
276 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
277 if (!spdifrx)
278 return -ENOMEM;
279
280 spdifrx->reset = devm_reset_control_get(&pdev->dev, "spdifrx-m");
281 if (IS_ERR(spdifrx->reset)) {
282 ret = PTR_ERR(spdifrx->reset);
283 if (ret != -ENOENT)
284 return ret;
285 }
286
287 spdifrx->hclk = devm_clk_get(&pdev->dev, "hclk");
288 if (IS_ERR(spdifrx->hclk))
289 return PTR_ERR(spdifrx->hclk);
290
291 spdifrx->mclk = devm_clk_get(&pdev->dev, "mclk");
292 if (IS_ERR(spdifrx->mclk))
293 return PTR_ERR(spdifrx->mclk);
294
295 spdifrx->irq = platform_get_irq(pdev, 0);
296 if (spdifrx->irq < 0)
297 return spdifrx->irq;
298
299 ret = devm_request_threaded_irq(&pdev->dev, spdifrx->irq, NULL,
300 rk_spdifrx_isr,
301 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
302 dev_name(&pdev->dev), spdifrx);
303 if (ret)
304 return ret;
305
306 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
307 regs = devm_ioremap_resource(&pdev->dev, res);
308 if (IS_ERR(regs))
309 return PTR_ERR(regs);
310
311 spdifrx->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
312 &rk_spdifrx_regmap_config);
313 if (IS_ERR(spdifrx->regmap))
314 return PTR_ERR(spdifrx->regmap);
315
316 spdifrx->capture_dma_data.addr = res->start + SPDIFRX_SMPDR;
317 spdifrx->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
318 spdifrx->capture_dma_data.maxburst = 4;
319
320 spdifrx->dev = &pdev->dev;
321 dev_set_drvdata(&pdev->dev, spdifrx);
322
323 pm_runtime_enable(&pdev->dev);
324 if (!pm_runtime_enabled(&pdev->dev)) {
325 ret = rk_spdifrx_runtime_resume(&pdev->dev);
326 if (ret)
327 goto err_pm_runtime;
328 }
329
330 ret = devm_snd_soc_register_component(&pdev->dev,
331 &rk_spdifrx_component,
332 &rk_spdifrx_dai, 1);
333 if (ret) {
334 dev_err(&pdev->dev, "Could not register DAI\n");
335 goto err_pm_suspend;
336 }
337
338 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
339 if (ret) {
340 dev_err(&pdev->dev, "Could not register PCM\n");
341 goto err_pm_suspend;
342 }
343
344 return 0;
345
346 err_pm_suspend:
347 if (!pm_runtime_status_suspended(&pdev->dev))
348 rk_spdifrx_runtime_suspend(&pdev->dev);
349 err_pm_runtime:
350 pm_runtime_disable(&pdev->dev);
351
352 return ret;
353 }
354
rk_spdifrx_remove(struct platform_device * pdev)355 static int rk_spdifrx_remove(struct platform_device *pdev)
356 {
357 pm_runtime_disable(&pdev->dev);
358 if (!pm_runtime_status_suspended(&pdev->dev))
359 rk_spdifrx_runtime_suspend(&pdev->dev);
360
361 return 0;
362 }
363
364 #ifdef CONFIG_PM_SLEEP
rockchip_spdifrx_suspend(struct device * dev)365 static int rockchip_spdifrx_suspend(struct device *dev)
366 {
367 struct rk_spdifrx_dev *spdifrx = dev_get_drvdata(dev);
368
369 regcache_mark_dirty(spdifrx->regmap);
370
371 return 0;
372 }
373
rockchip_spdifrx_resume(struct device * dev)374 static int rockchip_spdifrx_resume(struct device *dev)
375 {
376 struct rk_spdifrx_dev *spdifrx = dev_get_drvdata(dev);
377 int ret;
378
379 ret = pm_runtime_get_sync(dev);
380 if (ret < 0)
381 return ret;
382 ret = regcache_sync(spdifrx->regmap);
383 pm_runtime_put(dev);
384
385 return ret;
386 }
387 #endif
388
389 static const struct dev_pm_ops rk_spdifrx_pm_ops = {
390 SET_RUNTIME_PM_OPS(rk_spdifrx_runtime_suspend, rk_spdifrx_runtime_resume,
391 NULL)
392 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spdifrx_suspend, rockchip_spdifrx_resume)
393 };
394
395 static const struct of_device_id rk_spdifrx_match[] = {
396 { .compatible = "rockchip,rk3308-spdifrx", },
397 {},
398 };
399 MODULE_DEVICE_TABLE(of, rk_spdifrx_match);
400
401 static struct platform_driver rk_spdifrx_driver = {
402 .probe = rk_spdifrx_probe,
403 .remove = rk_spdifrx_remove,
404 .driver = {
405 .name = "rockchip-spdifrx",
406 .of_match_table = of_match_ptr(rk_spdifrx_match),
407 .pm = &rk_spdifrx_pm_ops,
408 },
409 };
410 module_platform_driver(rk_spdifrx_driver);
411
412 MODULE_ALIAS("platform:rockchip-spdifrx");
413 MODULE_DESCRIPTION("ROCKCHIP SPDIFRX Controller Interface");
414 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
415 MODULE_LICENSE("GPL v2");
416