1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2015 Collabora Ltd. 6*4882a593Smuzhiyun * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ROCKCHIP_SPDIF_H 10*4882a593Smuzhiyun #define _ROCKCHIP_SPDIF_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * CFGR 14*4882a593Smuzhiyun * transfer configuration register 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define SPDIF_CFGR_CLK_DIV_SHIFT (16) 17*4882a593Smuzhiyun #define SPDIF_CFGR_CLK_DIV_MASK (0xff << SPDIF_CFGR_CLK_DIV_SHIFT) 18*4882a593Smuzhiyun #define SPDIF_CFGR_CLK_DIV(x) ((x - 1) << SPDIF_CFGR_CLK_DIV_SHIFT) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define SPDIF_CFGR_CLR_MASK BIT(7) 21*4882a593Smuzhiyun #define SPDIF_CFGR_CLR_EN BIT(7) 22*4882a593Smuzhiyun #define SPDIF_CFGR_CLR_DIS 0 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define SPDIF_CFGR_CSE_MASK BIT(6) 25*4882a593Smuzhiyun #define SPDIF_CFGR_CSE_EN BIT(6) 26*4882a593Smuzhiyun #define SPDIF_CFGR_CSE_DIS 0 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define SPDIF_CFGR_ADJ_MASK BIT(3) 29*4882a593Smuzhiyun #define SPDIF_CFGR_ADJ_LEFT_J BIT(3) 30*4882a593Smuzhiyun #define SPDIF_CFGR_ADJ_RIGHT_J 0 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define SPDIF_CFGR_HALFWORD_SHIFT 2 33*4882a593Smuzhiyun #define SPDIF_CFGR_HALFWORD_DISABLE (0 << SPDIF_CFGR_HALFWORD_SHIFT) 34*4882a593Smuzhiyun #define SPDIF_CFGR_HALFWORD_ENABLE (1 << SPDIF_CFGR_HALFWORD_SHIFT) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define SPDIF_CFGR_VDW_SHIFT 0 37*4882a593Smuzhiyun #define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT) 38*4882a593Smuzhiyun #define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0) 41*4882a593Smuzhiyun #define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1) 42*4882a593Smuzhiyun #define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * DMACR 46*4882a593Smuzhiyun * DMA control register 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun #define SPDIF_DMACR_TDE_SHIFT 5 49*4882a593Smuzhiyun #define SPDIF_DMACR_TDE_DISABLE (0 << SPDIF_DMACR_TDE_SHIFT) 50*4882a593Smuzhiyun #define SPDIF_DMACR_TDE_ENABLE (1 << SPDIF_DMACR_TDE_SHIFT) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define SPDIF_DMACR_TDL_SHIFT 0 53*4882a593Smuzhiyun #define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT) 54*4882a593Smuzhiyun #define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * XFER 58*4882a593Smuzhiyun * Transfer control register 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define SPDIF_XFER_TXS_SHIFT 0 61*4882a593Smuzhiyun #define SPDIF_XFER_TXS_STOP (0 << SPDIF_XFER_TXS_SHIFT) 62*4882a593Smuzhiyun #define SPDIF_XFER_TXS_START (1 << SPDIF_XFER_TXS_SHIFT) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define SPDIF_CFGR (0x0000) 65*4882a593Smuzhiyun #define SPDIF_SDBLR (0x0004) 66*4882a593Smuzhiyun #define SPDIF_DMACR (0x0008) 67*4882a593Smuzhiyun #define SPDIF_INTCR (0x000c) 68*4882a593Smuzhiyun #define SPDIF_INTSR (0x0010) 69*4882a593Smuzhiyun #define SPDIF_XFER (0x0018) 70*4882a593Smuzhiyun #define SPDIF_SMPDR (0x0020) 71*4882a593Smuzhiyun #define SPDIF_VLDFRn(x) (0x0060 + (x) * 4) 72*4882a593Smuzhiyun #define SPDIF_USRDRn(x) (0x0090 + (x) * 4) 73*4882a593Smuzhiyun #define SPDIF_CHNSRn(x) (0x00c0 + (x) * 4) 74*4882a593Smuzhiyun #define SPDIF_VERSION (0x01c0) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* _ROCKCHIP_SPDIF_H */ 77