1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Rockchip PDM ALSA SoC Digital Audio Interface(DAI) driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ROCKCHIP_PDM_H 9*4882a593Smuzhiyun #define _ROCKCHIP_PDM_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* PDM REGS */ 12*4882a593Smuzhiyun #define PDM_SYSCONFIG (0x0000) 13*4882a593Smuzhiyun #define PDM_CTRL0 (0x0004) 14*4882a593Smuzhiyun #define PDM_CTRL1 (0x0008) 15*4882a593Smuzhiyun #define PDM_CLK_CTRL (0x000c) 16*4882a593Smuzhiyun #define PDM_HPF_CTRL (0x0010) 17*4882a593Smuzhiyun #define PDM_FIFO_CTRL (0x0014) 18*4882a593Smuzhiyun #define PDM_DMA_CTRL (0x0018) 19*4882a593Smuzhiyun #define PDM_INT_EN (0x001c) 20*4882a593Smuzhiyun #define PDM_INT_CLR (0x0020) 21*4882a593Smuzhiyun #define PDM_INT_ST (0x0024) 22*4882a593Smuzhiyun #define PDM_RXFIFO_DATA (0x0030) 23*4882a593Smuzhiyun #define PDM_DATA_VALID (0x0054) 24*4882a593Smuzhiyun #define PDM_VERSION (0x0058) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* PDM_SYSCONFIG */ 27*4882a593Smuzhiyun #define PDM_RX_MASK (0x1 << 2) 28*4882a593Smuzhiyun #define PDM_RX_START (0x1 << 2) 29*4882a593Smuzhiyun #define PDM_RX_STOP (0x0 << 2) 30*4882a593Smuzhiyun #define PDM_RX_CLR_MASK (0x1 << 0) 31*4882a593Smuzhiyun #define PDM_RX_CLR_WR (0x1 << 0) 32*4882a593Smuzhiyun #define PDM_RX_CLR_DONE (0x0 << 0) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* PDM CTRL0 */ 35*4882a593Smuzhiyun #define PDM_PATH_MSK (0xf << 27) 36*4882a593Smuzhiyun #define PDM_MODE_MSK BIT(31) 37*4882a593Smuzhiyun #define PDM_MODE_RJ 0 38*4882a593Smuzhiyun #define PDM_MODE_LJ BIT(31) 39*4882a593Smuzhiyun #define PDM_PATH3_EN BIT(30) 40*4882a593Smuzhiyun #define PDM_PATH2_EN BIT(29) 41*4882a593Smuzhiyun #define PDM_PATH1_EN BIT(28) 42*4882a593Smuzhiyun #define PDM_PATH0_EN BIT(27) 43*4882a593Smuzhiyun #define PDM_HWT_EN BIT(26) 44*4882a593Smuzhiyun #define PDM_SAMPLERATE_MSK GENMASK(7, 5) 45*4882a593Smuzhiyun #define PDM_SAMPLERATE(x) ((x) << 5) 46*4882a593Smuzhiyun #define PDM_VDW_MSK (0x1f << 0) 47*4882a593Smuzhiyun #define PDM_VDW(X) ((X - 1) << 0) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* PDM CTRL1 */ 50*4882a593Smuzhiyun #define PDM_FD_NUMERATOR_SFT 16 51*4882a593Smuzhiyun #define PDM_FD_NUMERATOR_MSK GENMASK(31, 16) 52*4882a593Smuzhiyun #define PDM_FD_DENOMINATOR_SFT 0 53*4882a593Smuzhiyun #define PDM_FD_DENOMINATOR_MSK GENMASK(15, 0) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* PDM CLK CTRL */ 56*4882a593Smuzhiyun #define PDM_PATH_SHIFT(x) (8 + (x) * 2) 57*4882a593Smuzhiyun #define PDM_PATH_MASK(x) (0x3 << PDM_PATH_SHIFT(x)) 58*4882a593Smuzhiyun #define PDM_PATH(x, v) ((v) << PDM_PATH_SHIFT(x)) 59*4882a593Smuzhiyun #define PDM_CLK_FD_RATIO_MSK BIT(6) 60*4882a593Smuzhiyun #define PDM_CLK_FD_RATIO_40 (0X0 << 6) 61*4882a593Smuzhiyun #define PDM_CLK_FD_RATIO_35 BIT(6) 62*4882a593Smuzhiyun #define PDM_CLK_MSK BIT(5) 63*4882a593Smuzhiyun #define PDM_CLK_EN BIT(5) 64*4882a593Smuzhiyun #define PDM_CLK_DIS (0x0 << 5) 65*4882a593Smuzhiyun #define PDM_CKP_MSK BIT(3) 66*4882a593Smuzhiyun #define PDM_CKP_NORMAL (0x0 << 3) 67*4882a593Smuzhiyun #define PDM_CKP_INVERTED BIT(3) 68*4882a593Smuzhiyun #define PDM_DS_RATIO_MSK (0x7 << 0) 69*4882a593Smuzhiyun #define PDM_CLK_320FS (0x0 << 0) 70*4882a593Smuzhiyun #define PDM_CLK_640FS (0x1 << 0) 71*4882a593Smuzhiyun #define PDM_CLK_1280FS (0x2 << 0) 72*4882a593Smuzhiyun #define PDM_CLK_2560FS (0x3 << 0) 73*4882a593Smuzhiyun #define PDM_CLK_5120FS (0x4 << 0) 74*4882a593Smuzhiyun #define PDM_CIC_RATIO_MSK (0x3 << 0) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* PDM HPF CTRL */ 77*4882a593Smuzhiyun #define PDM_HPF_LE BIT(3) 78*4882a593Smuzhiyun #define PDM_HPF_RE BIT(2) 79*4882a593Smuzhiyun #define PDM_HPF_CF_MSK (0x3 << 0) 80*4882a593Smuzhiyun #define PDM_HPF_3P79HZ (0x0 << 0) 81*4882a593Smuzhiyun #define PDM_HPF_60HZ (0x1 << 0) 82*4882a593Smuzhiyun #define PDM_HPF_243HZ (0x2 << 0) 83*4882a593Smuzhiyun #define PDM_HPF_493HZ (0x3 << 0) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* PDM FIFO CTRL */ 86*4882a593Smuzhiyun #define PDM_FIFO_CNT(x) ((x) & 0xff) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* PDM DMA CTRL */ 89*4882a593Smuzhiyun #define PDM_DMA_RD_MSK BIT(8) 90*4882a593Smuzhiyun #define PDM_DMA_RD_EN BIT(8) 91*4882a593Smuzhiyun #define PDM_DMA_RD_DIS (0x0 << 8) 92*4882a593Smuzhiyun #define PDM_DMA_RDL_MSK (0x7f << 0) 93*4882a593Smuzhiyun #define PDM_DMA_RDL(X) ((X - 1) << 0) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif /* _ROCKCHIP_PDM_H */ 96