1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip PDM ALSA SoC Digital Audio Interface(DAI) driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
6 */
7
8 #include <linux/module.h>
9 #include <linux/clk.h>
10 #include <linux/clk/rockchip.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/pinctrl/consumer.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/rational.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm_params.h>
20
21 #include "rockchip_pdm.h"
22
23 #define PDM_DMA_BURST_SIZE (8) /* size * width: 8*4 = 32 bytes */
24 #define PDM_SIGNOFF_CLK_100M (100000000)
25 #define PDM_SIGNOFF_CLK_300M (300000000)
26 #define PDM_PATH_MAX (4)
27 #define PDM_DEFAULT_RATE (48000)
28 #define PDM_START_DELAY_MS_DEFAULT (20)
29 #define PDM_START_DELAY_MS_MIN (0)
30 #define PDM_START_DELAY_MS_MAX (1000)
31 #define PDM_FILTER_DELAY_MS_MIN (20)
32 #define PDM_FILTER_DELAY_MS_MAX (1000)
33 #define PDM_CLK_SHIFT_PPM_MAX (1000000) /* 1 ppm */
34 #define CLK_PPM_MIN (-1000)
35 #define CLK_PPM_MAX (1000)
36
37 enum rk_pdm_version {
38 RK_PDM_RK3229,
39 RK_PDM_RK3308,
40 RK_PDM_RK3588,
41 RK_PDM_RV1126,
42 };
43
44 struct rk_pdm_dev {
45 struct device *dev;
46 struct clk *clk;
47 struct clk *clk_root;
48 struct clk *hclk;
49 struct regmap *regmap;
50 struct snd_dmaengine_dai_dma_data capture_dma_data;
51 struct reset_control *reset;
52 struct pinctrl *pinctrl;
53 struct pinctrl_state *clk_state;
54 unsigned int start_delay_ms;
55 unsigned int filter_delay_ms;
56 enum rk_pdm_version version;
57 unsigned int clk_root_rate;
58 unsigned int clk_root_initial_rate;
59 int clk_ppm;
60 bool clk_calibrate;
61 };
62
63 struct rk_pdm_clkref {
64 unsigned int sr;
65 unsigned int clk;
66 unsigned int clk_out;
67 };
68
69 struct rk_pdm_ds_ratio {
70 unsigned int ratio;
71 unsigned int sr;
72 };
73
74 static struct rk_pdm_clkref clkref[] = {
75 { 8000, 40960000, 2048000 },
76 { 11025, 56448000, 2822400 },
77 { 12000, 61440000, 3072000 },
78 { 8000, 98304000, 2048000 },
79 { 12000, 98304000, 3072000 },
80 };
81
82 static struct rk_pdm_ds_ratio ds_ratio[] = {
83 { 0, 192000 },
84 { 0, 176400 },
85 { 0, 128000 },
86 { 1, 96000 },
87 { 1, 88200 },
88 { 1, 64000 },
89 { 2, 48000 },
90 { 2, 44100 },
91 { 2, 32000 },
92 { 3, 24000 },
93 { 3, 22050 },
94 { 3, 16000 },
95 { 4, 12000 },
96 { 4, 11025 },
97 { 4, 8000 },
98 };
99
get_pdm_clk(struct rk_pdm_dev * pdm,unsigned int sr,unsigned int * clk_src,unsigned int * clk_out,unsigned int signoff)100 static unsigned int get_pdm_clk(struct rk_pdm_dev *pdm, unsigned int sr,
101 unsigned int *clk_src, unsigned int *clk_out,
102 unsigned int signoff)
103 {
104 unsigned int i, count, clk, div, rate, delta;
105
106 clk = 0;
107 if (!sr)
108 return clk;
109
110 count = ARRAY_SIZE(clkref);
111 for (i = 0; i < count; i++) {
112 if (sr % clkref[i].sr)
113 continue;
114 div = sr / clkref[i].sr;
115 if ((div & (div - 1)) == 0) {
116 *clk_out = clkref[i].clk_out;
117 if (pdm->clk_calibrate) {
118 clk = clkref[i].clk;
119 *clk_src = clk;
120 break;
121 }
122 rate = clk_round_rate(pdm->clk, clkref[i].clk);
123 delta = clkref[i].clk / PDM_CLK_SHIFT_PPM_MAX;
124 if (rate < clkref[i].clk - delta ||
125 rate > clkref[i].clk + delta)
126 continue;
127 clk = clkref[i].clk;
128 *clk_src = clkref[i].clk;
129 break;
130 }
131 }
132
133 if (!clk) {
134 clk = clk_round_rate(pdm->clk, signoff);
135 *clk_src = clk;
136 }
137 return clk;
138 }
139
get_pdm_ds_ratio(unsigned int sr)140 static unsigned int get_pdm_ds_ratio(unsigned int sr)
141 {
142 unsigned int i, count, ratio;
143
144 ratio = 0;
145 if (!sr)
146 return ratio;
147
148 count = ARRAY_SIZE(ds_ratio);
149 for (i = 0; i < count; i++) {
150 if (sr == ds_ratio[i].sr)
151 ratio = ds_ratio[i].ratio;
152 }
153 return ratio;
154 }
155
get_pdm_cic_ratio(unsigned int clk)156 static unsigned int get_pdm_cic_ratio(unsigned int clk)
157 {
158 switch (clk) {
159 case 4096000:
160 case 5644800:
161 case 6144000:
162 return 0;
163 case 2048000:
164 case 2822400:
165 case 3072000:
166 return 1;
167 case 1024000:
168 case 1411200:
169 case 1536000:
170 return 2;
171 default:
172 return 1;
173 }
174 }
175
samplerate_to_bit(unsigned int samplerate)176 static unsigned int samplerate_to_bit(unsigned int samplerate)
177 {
178 switch (samplerate) {
179 case 8000:
180 case 11025:
181 case 12000:
182 return 0;
183 case 16000:
184 case 22050:
185 case 24000:
186 return 1;
187 case 32000:
188 return 2;
189 case 44100:
190 case 48000:
191 return 3;
192 case 64000:
193 case 88200:
194 case 96000:
195 return 4;
196 case 128000:
197 case 176400:
198 case 192000:
199 return 5;
200 default:
201 return 1;
202 }
203 }
204
to_info(struct snd_soc_dai * dai)205 static inline struct rk_pdm_dev *to_info(struct snd_soc_dai *dai)
206 {
207 return snd_soc_dai_get_drvdata(dai);
208 }
209
rockchip_pdm_rxctrl(struct rk_pdm_dev * pdm,int on)210 static void rockchip_pdm_rxctrl(struct rk_pdm_dev *pdm, int on)
211 {
212 unsigned long flags;
213
214 if (on) {
215 /* The PDM device need to delete some unused data
216 * since the pdm of various manufacturers can not
217 * be stable quickly. This is done by commit "ASoC:
218 * rockchip: pdm: Fix pop noise in the beginning".
219 *
220 * But we do not know how many data we delete, this
221 * cause channel disorder. For example, we record
222 * two channel 24-bit sound, then delete some starting
223 * data. Because the deleted starting data is uncertain,
224 * the next data may be left or right channel and cause
225 * channel disorder.
226 *
227 * Luckily, we can use the PDM_RX_CLR to fix this.
228 * Use the PDM_RX_CLR to clear fifo written data and
229 * address, but can not clear the read data and address.
230 * In initial state, the read data and address are zero.
231 */
232 local_irq_save(flags);
233 regmap_update_bits(pdm->regmap, PDM_SYSCONFIG,
234 PDM_RX_CLR_MASK,
235 PDM_RX_CLR_WR);
236 regmap_update_bits(pdm->regmap, PDM_DMA_CTRL,
237 PDM_DMA_RD_MSK, PDM_DMA_RD_EN);
238 local_irq_restore(flags);
239 } else {
240 regmap_update_bits(pdm->regmap, PDM_DMA_CTRL,
241 PDM_DMA_RD_MSK, PDM_DMA_RD_DIS);
242 regmap_update_bits(pdm->regmap, PDM_SYSCONFIG,
243 PDM_RX_MASK | PDM_RX_CLR_MASK,
244 PDM_RX_STOP | PDM_RX_CLR_WR);
245 }
246 }
247
rockchip_pdm_clk_set_rate(struct rk_pdm_dev * pdm,struct clk * clk,unsigned long rate,int ppm)248 static int rockchip_pdm_clk_set_rate(struct rk_pdm_dev *pdm,
249 struct clk *clk, unsigned long rate,
250 int ppm)
251 {
252 unsigned long rate_target;
253 int delta, ret;
254
255 if (ppm == pdm->clk_ppm)
256 return 0;
257
258 ret = rockchip_pll_clk_compensation(clk, ppm);
259 if (ret != -ENOSYS)
260 goto out;
261
262 delta = (ppm < 0) ? -1 : 1;
263 delta *= (int)div64_u64((uint64_t)rate * (uint64_t)abs(ppm) + 500000, 1000000);
264
265 rate_target = rate + delta;
266
267 if (!rate_target)
268 return -EINVAL;
269
270 ret = clk_set_rate(clk, rate_target);
271 if (ret)
272 return ret;
273 out:
274 if (!ret)
275 pdm->clk_ppm = ppm;
276
277 return ret;
278 }
279
rockchip_pdm_set_samplerate(struct rk_pdm_dev * pdm,unsigned int samplerate)280 static int rockchip_pdm_set_samplerate(struct rk_pdm_dev *pdm, unsigned int samplerate)
281 {
282
283 unsigned int val = 0, div = 0;
284 unsigned int clk_rate, clk_div, rate, delta;
285 unsigned int clk_src = 0, clk_out = 0, signoff = PDM_SIGNOFF_CLK_100M;
286 unsigned long m, n;
287 uint64_t ppm;
288 bool change;
289 int ret;
290
291 if (pdm->version == RK_PDM_RK3588)
292 signoff = PDM_SIGNOFF_CLK_300M;
293 clk_rate = get_pdm_clk(pdm, samplerate, &clk_src, &clk_out, signoff);
294 if (!clk_rate)
295 return -EINVAL;
296
297 if (pdm->clk_calibrate) {
298 ret = clk_set_parent(pdm->clk, pdm->clk_root);
299 if (ret)
300 return ret;
301
302 ret = rockchip_pdm_clk_set_rate(pdm, pdm->clk_root,
303 pdm->clk_root_rate, 0);
304 if (ret)
305 return ret;
306
307 rate = pdm->clk_root_rate;
308 delta = abs(rate % clk_src - clk_src);
309 ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)rate);
310
311 if (ppm) {
312 div = DIV_ROUND_CLOSEST(pdm->clk_root_initial_rate, clk_src);
313 if (!div)
314 return -EINVAL;
315
316 rate = clk_src * round_up(div, 2);
317 ret = clk_set_rate(pdm->clk_root, rate);
318 if (ret)
319 return ret;
320
321 pdm->clk_root_rate = clk_get_rate(pdm->clk_root);
322 }
323 }
324
325 ret = clk_set_rate(pdm->clk, clk_src);
326 if (ret)
327 return ret;
328
329 if (pdm->version == RK_PDM_RK3308 ||
330 pdm->version == RK_PDM_RK3588 ||
331 pdm->version == RK_PDM_RV1126) {
332 rational_best_approximation(clk_out, clk_src,
333 GENMASK(16 - 1, 0),
334 GENMASK(16 - 1, 0),
335 &m, &n);
336
337 val = (m << PDM_FD_NUMERATOR_SFT) |
338 (n << PDM_FD_DENOMINATOR_SFT);
339 regmap_update_bits_check(pdm->regmap, PDM_CTRL1,
340 PDM_FD_NUMERATOR_MSK |
341 PDM_FD_DENOMINATOR_MSK,
342 val, &change);
343 if (change) {
344 reset_control_assert(pdm->reset);
345 reset_control_deassert(pdm->reset);
346 rockchip_pdm_rxctrl(pdm, 0);
347 }
348 clk_div = n / m;
349 if (clk_div >= 40)
350 val = PDM_CLK_FD_RATIO_40;
351 else if (clk_div <= 35)
352 val = PDM_CLK_FD_RATIO_35;
353 else
354 return -EINVAL;
355 regmap_update_bits(pdm->regmap, PDM_CLK_CTRL,
356 PDM_CLK_FD_RATIO_MSK,
357 val);
358 }
359
360 if (pdm->version == RK_PDM_RK3588 || pdm->version == RK_PDM_RV1126) {
361 val = get_pdm_cic_ratio(clk_out);
362 regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CIC_RATIO_MSK, val);
363 val = samplerate_to_bit(samplerate);
364 regmap_update_bits(pdm->regmap, PDM_CTRL0,
365 PDM_SAMPLERATE_MSK, PDM_SAMPLERATE(val));
366 } else {
367 val = get_pdm_ds_ratio(samplerate);
368 regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val);
369 }
370
371 regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
372 PDM_HPF_CF_MSK, PDM_HPF_60HZ);
373 regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
374 PDM_HPF_LE | PDM_HPF_RE, PDM_HPF_LE | PDM_HPF_RE);
375 return 0;
376 }
377
rockchip_pdm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)378 static int rockchip_pdm_hw_params(struct snd_pcm_substream *substream,
379 struct snd_pcm_hw_params *params,
380 struct snd_soc_dai *dai)
381 {
382 struct rk_pdm_dev *pdm = to_info(dai);
383 unsigned int val = 0;
384
385 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
386 return 0;
387
388 rockchip_pdm_set_samplerate(pdm, params_rate(params));
389
390 if (pdm->version != RK_PDM_RK3229)
391 regmap_update_bits(pdm->regmap, PDM_CTRL0,
392 PDM_MODE_MSK, PDM_MODE_LJ);
393
394 val = 0;
395 switch (params_format(params)) {
396 case SNDRV_PCM_FORMAT_S8:
397 val |= PDM_VDW(8);
398 break;
399 case SNDRV_PCM_FORMAT_S16_LE:
400 val |= PDM_VDW(16);
401 break;
402 case SNDRV_PCM_FORMAT_S20_3LE:
403 val |= PDM_VDW(20);
404 break;
405 case SNDRV_PCM_FORMAT_S24_LE:
406 val |= PDM_VDW(24);
407 break;
408 case SNDRV_PCM_FORMAT_S32_LE:
409 val |= PDM_VDW(32);
410 break;
411 default:
412 return -EINVAL;
413 }
414
415 switch (params_channels(params)) {
416 case 8:
417 val |= PDM_PATH3_EN;
418 fallthrough;
419 case 6:
420 val |= PDM_PATH2_EN;
421 fallthrough;
422 case 4:
423 val |= PDM_PATH1_EN;
424 fallthrough;
425 case 2:
426 val |= PDM_PATH0_EN;
427 break;
428 default:
429 dev_err(pdm->dev, "invalid channel: %d\n",
430 params_channels(params));
431 return -EINVAL;
432 }
433
434 regmap_update_bits(pdm->regmap, PDM_CTRL0,
435 PDM_PATH_MSK | PDM_VDW_MSK,
436 val);
437 /* all channels share the single FIFO */
438 regmap_update_bits(pdm->regmap, PDM_DMA_CTRL, PDM_DMA_RDL_MSK,
439 PDM_DMA_RDL(8 * params_channels(params)));
440
441 return 0;
442 }
443
rockchip_pdm_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)444 static int rockchip_pdm_set_fmt(struct snd_soc_dai *cpu_dai,
445 unsigned int fmt)
446 {
447 struct rk_pdm_dev *pdm = to_info(cpu_dai);
448 unsigned int mask = 0, val = 0;
449
450 mask = PDM_CKP_MSK;
451 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
452 case SND_SOC_DAIFMT_NB_NF:
453 val = PDM_CKP_NORMAL;
454 break;
455 case SND_SOC_DAIFMT_IB_NF:
456 val = PDM_CKP_INVERTED;
457 break;
458 default:
459 return -EINVAL;
460 }
461
462 pm_runtime_get_sync(cpu_dai->dev);
463 regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, mask, val);
464 pm_runtime_put(cpu_dai->dev);
465
466 return 0;
467 }
468
rockchip_pdm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)469 static int rockchip_pdm_trigger(struct snd_pcm_substream *substream, int cmd,
470 struct snd_soc_dai *dai)
471 {
472 struct rk_pdm_dev *pdm = to_info(dai);
473 int ret = 0;
474
475 switch (cmd) {
476 case SNDRV_PCM_TRIGGER_START:
477 case SNDRV_PCM_TRIGGER_RESUME:
478 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
479 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
480 rockchip_pdm_rxctrl(pdm, 1);
481 break;
482 case SNDRV_PCM_TRIGGER_SUSPEND:
483 case SNDRV_PCM_TRIGGER_STOP:
484 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
485 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
486 rockchip_pdm_rxctrl(pdm, 0);
487 break;
488 default:
489 ret = -EINVAL;
490 break;
491 }
492
493 return ret;
494 }
495
rockchip_pdm_start_delay_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)496 static int rockchip_pdm_start_delay_info(struct snd_kcontrol *kcontrol,
497 struct snd_ctl_elem_info *uinfo)
498 {
499 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
500 uinfo->count = 1;
501 uinfo->value.integer.min = PDM_START_DELAY_MS_MIN;
502 uinfo->value.integer.max = PDM_START_DELAY_MS_MAX;
503 uinfo->value.integer.step = 1;
504
505 return 0;
506 }
507
rockchip_pdm_start_delay_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)508 static int rockchip_pdm_start_delay_get(struct snd_kcontrol *kcontrol,
509 struct snd_ctl_elem_value *ucontrol)
510 {
511 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
512 struct rk_pdm_dev *pdm = snd_soc_dai_get_drvdata(dai);
513
514 ucontrol->value.integer.value[0] = pdm->start_delay_ms;
515
516 return 0;
517 }
518
rockchip_pdm_start_delay_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)519 static int rockchip_pdm_start_delay_put(struct snd_kcontrol *kcontrol,
520 struct snd_ctl_elem_value *ucontrol)
521 {
522 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
523 struct rk_pdm_dev *pdm = snd_soc_dai_get_drvdata(dai);
524
525 if ((ucontrol->value.integer.value[0] < PDM_START_DELAY_MS_MIN) ||
526 (ucontrol->value.integer.value[0] > PDM_START_DELAY_MS_MAX))
527 return -EINVAL;
528
529 pdm->start_delay_ms = ucontrol->value.integer.value[0];
530
531 return 1;
532 }
533
rockchip_pdm_filter_delay_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)534 static int rockchip_pdm_filter_delay_info(struct snd_kcontrol *kcontrol,
535 struct snd_ctl_elem_info *uinfo)
536 {
537 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
538 uinfo->count = 1;
539 uinfo->value.integer.min = PDM_FILTER_DELAY_MS_MIN;
540 uinfo->value.integer.max = PDM_FILTER_DELAY_MS_MAX;
541 uinfo->value.integer.step = 1;
542
543 return 0;
544 }
545
rockchip_pdm_filter_delay_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)546 static int rockchip_pdm_filter_delay_get(struct snd_kcontrol *kcontrol,
547 struct snd_ctl_elem_value *ucontrol)
548 {
549 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
550 struct rk_pdm_dev *pdm = snd_soc_dai_get_drvdata(dai);
551
552 ucontrol->value.integer.value[0] = pdm->filter_delay_ms;
553
554 return 0;
555 }
556
rockchip_pdm_filter_delay_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)557 static int rockchip_pdm_filter_delay_put(struct snd_kcontrol *kcontrol,
558 struct snd_ctl_elem_value *ucontrol)
559 {
560 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
561 struct rk_pdm_dev *pdm = snd_soc_dai_get_drvdata(dai);
562
563 if ((ucontrol->value.integer.value[0] < PDM_FILTER_DELAY_MS_MIN) ||
564 (ucontrol->value.integer.value[0] > PDM_FILTER_DELAY_MS_MAX))
565 return -EINVAL;
566
567 pdm->filter_delay_ms = ucontrol->value.integer.value[0];
568
569 return 1;
570 }
571
572 static const struct snd_kcontrol_new rockchip_pdm_controls[] = {
573 {
574 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
575 .name = "PDM Start Delay Ms",
576 .info = rockchip_pdm_start_delay_info,
577 .get = rockchip_pdm_start_delay_get,
578 .put = rockchip_pdm_start_delay_put,
579 },
580 {
581 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
582 .name = "PDM Filter Delay Ms",
583 .info = rockchip_pdm_filter_delay_info,
584 .get = rockchip_pdm_filter_delay_get,
585 .put = rockchip_pdm_filter_delay_put,
586 },
587 };
588
rockchip_pdm_clk_compensation_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)589 static int rockchip_pdm_clk_compensation_info(struct snd_kcontrol *kcontrol,
590 struct snd_ctl_elem_info *uinfo)
591 {
592 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
593 uinfo->count = 1;
594 uinfo->value.integer.min = CLK_PPM_MIN;
595 uinfo->value.integer.max = CLK_PPM_MAX;
596 uinfo->value.integer.step = 1;
597
598 return 0;
599 }
600
601
rockchip_pdm_clk_compensation_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)602 static int rockchip_pdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
603 struct snd_ctl_elem_value *ucontrol)
604
605 {
606 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
607 struct rk_pdm_dev *pdm = snd_soc_dai_get_drvdata(dai);
608
609 ucontrol->value.integer.value[0] = pdm->clk_ppm;
610
611 return 0;
612 }
613
rockchip_pdm_clk_compensation_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)614 static int rockchip_pdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
615 struct snd_ctl_elem_value *ucontrol)
616 {
617 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
618 struct rk_pdm_dev *pdm = snd_soc_dai_get_drvdata(dai);
619
620 int ppm = ucontrol->value.integer.value[0];
621
622 if ((ucontrol->value.integer.value[0] < CLK_PPM_MIN) ||
623 (ucontrol->value.integer.value[0] > CLK_PPM_MAX))
624 return -EINVAL;
625
626 return rockchip_pdm_clk_set_rate(pdm, pdm->clk_root, pdm->clk_root_rate, ppm);
627 }
628
629 static struct snd_kcontrol_new rockchip_pdm_compensation_control = {
630 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
631 .name = "PDM PCM Clk Compensation In PPM",
632 .info = rockchip_pdm_clk_compensation_info,
633 .get = rockchip_pdm_clk_compensation_get,
634 .put = rockchip_pdm_clk_compensation_put,
635
636 };
637
rockchip_pdm_dai_probe(struct snd_soc_dai * dai)638 static int rockchip_pdm_dai_probe(struct snd_soc_dai *dai)
639 {
640 struct rk_pdm_dev *pdm = to_info(dai);
641
642 dai->capture_dma_data = &pdm->capture_dma_data;
643 snd_soc_add_dai_controls(dai, rockchip_pdm_controls,
644 ARRAY_SIZE(rockchip_pdm_controls));
645 if (pdm->clk_calibrate)
646 snd_soc_add_dai_controls(dai, &rockchip_pdm_compensation_control, 1);
647 return 0;
648 }
649
rockchip_pdm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)650 static void rockchip_pdm_shutdown(struct snd_pcm_substream *substream,
651 struct snd_soc_dai *dai)
652 {
653 struct rk_pdm_dev *pdm = to_info(dai);
654
655 if (substream->stream != SNDRV_PCM_STREAM_CAPTURE)
656 return;
657
658 regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CLK_MSK, PDM_CLK_DIS);
659 }
660
rockchip_pdm_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)661 static int rockchip_pdm_prepare(struct snd_pcm_substream *substream,
662 struct snd_soc_dai *dai)
663 {
664 struct rk_pdm_dev *pdm = to_info(dai);
665
666 if (substream->stream != SNDRV_PCM_STREAM_CAPTURE)
667 return 0;
668
669 regmap_update_bits(pdm->regmap, PDM_SYSCONFIG, PDM_RX_MASK, PDM_RX_START);
670 /*
671 * after xfer start, a necessary delay for filter to init and will drop
672 * the dirty data in the trigger-START late.
673 */
674 usleep_range((pdm->filter_delay_ms) * 1000, (pdm->filter_delay_ms + 1) * 1000);
675
676 return 0;
677 }
678
rockchip_pdm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)679 static int rockchip_pdm_startup(struct snd_pcm_substream *substream,
680 struct snd_soc_dai *dai)
681 {
682 struct rk_pdm_dev *pdm = to_info(dai);
683
684 if (substream->stream != SNDRV_PCM_STREAM_CAPTURE)
685 return 0;
686
687 regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CLK_MSK, PDM_CLK_EN);
688 /*
689 * a necessary delay for dmics wake-up after clk enabled, and drop the
690 * dirty data in this duration.
691 */
692 usleep_range((pdm->start_delay_ms + 1) * 1000, (pdm->start_delay_ms + 2) * 1000);
693
694 return 0;
695 }
696
697 static const struct snd_soc_dai_ops rockchip_pdm_dai_ops = {
698 .startup = rockchip_pdm_startup,
699 .shutdown = rockchip_pdm_shutdown,
700 .set_fmt = rockchip_pdm_set_fmt,
701 .trigger = rockchip_pdm_trigger,
702 .prepare = rockchip_pdm_prepare,
703 .hw_params = rockchip_pdm_hw_params,
704 };
705
706 #define ROCKCHIP_PDM_RATES SNDRV_PCM_RATE_8000_192000
707 #define ROCKCHIP_PDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
708 SNDRV_PCM_FMTBIT_S20_3LE | \
709 SNDRV_PCM_FMTBIT_S24_LE | \
710 SNDRV_PCM_FMTBIT_S32_LE)
711
712 static struct snd_soc_dai_driver rockchip_pdm_dai = {
713 .probe = rockchip_pdm_dai_probe,
714 .capture = {
715 .stream_name = "Capture",
716 .channels_min = 2,
717 .channels_max = 8,
718 .rates = ROCKCHIP_PDM_RATES,
719 .formats = ROCKCHIP_PDM_FORMATS,
720 },
721 .ops = &rockchip_pdm_dai_ops,
722 .symmetric_rates = 1,
723 };
724
725 static const struct snd_soc_component_driver rockchip_pdm_component = {
726 .name = "rockchip-pdm",
727 };
728
rockchip_pdm_pinctrl_select_clk_state(struct device * dev)729 static int rockchip_pdm_pinctrl_select_clk_state(struct device *dev)
730 {
731 struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
732
733 if (IS_ERR_OR_NULL(pdm->pinctrl) || !pdm->clk_state)
734 return 0;
735
736 /*
737 * A necessary delay to make sure the correct
738 * frac div has been applied when resume from
739 * power down.
740 */
741 udelay(10);
742
743 /*
744 * Must disable the clk to avoid clk glitch
745 * when pinctrl switch from gpio to pdm clk.
746 */
747 clk_disable_unprepare(pdm->clk);
748 pinctrl_select_state(pdm->pinctrl, pdm->clk_state);
749 clk_prepare_enable(pdm->clk);
750
751 return 0;
752 }
753
rockchip_pdm_runtime_suspend(struct device * dev)754 static int rockchip_pdm_runtime_suspend(struct device *dev)
755 {
756 struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
757
758 regcache_cache_only(pdm->regmap, true);
759 clk_disable_unprepare(pdm->clk);
760 clk_disable_unprepare(pdm->hclk);
761
762 pinctrl_pm_select_idle_state(dev);
763
764 return 0;
765 }
766
rockchip_pdm_runtime_resume(struct device * dev)767 static int rockchip_pdm_runtime_resume(struct device *dev)
768 {
769 struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
770 int ret;
771
772 ret = clk_prepare_enable(pdm->clk);
773 if (ret)
774 goto err_clk;
775
776 ret = clk_prepare_enable(pdm->hclk);
777 if (ret)
778 goto err_hclk;
779
780 regcache_cache_only(pdm->regmap, false);
781 regcache_mark_dirty(pdm->regmap);
782 ret = regcache_sync(pdm->regmap);
783 if (ret)
784 goto err_regmap;
785
786 rockchip_pdm_rxctrl(pdm, 0);
787
788 rockchip_pdm_pinctrl_select_clk_state(dev);
789
790 return 0;
791
792 err_regmap:
793 clk_disable_unprepare(pdm->hclk);
794 err_hclk:
795 clk_disable_unprepare(pdm->clk);
796 err_clk:
797 return ret;
798 }
799
rockchip_pdm_wr_reg(struct device * dev,unsigned int reg)800 static bool rockchip_pdm_wr_reg(struct device *dev, unsigned int reg)
801 {
802 switch (reg) {
803 case PDM_SYSCONFIG:
804 case PDM_CTRL0:
805 case PDM_CTRL1:
806 case PDM_CLK_CTRL:
807 case PDM_HPF_CTRL:
808 case PDM_FIFO_CTRL:
809 case PDM_DMA_CTRL:
810 case PDM_INT_EN:
811 case PDM_INT_CLR:
812 case PDM_DATA_VALID:
813 return true;
814 default:
815 return false;
816 }
817 }
818
rockchip_pdm_rd_reg(struct device * dev,unsigned int reg)819 static bool rockchip_pdm_rd_reg(struct device *dev, unsigned int reg)
820 {
821 switch (reg) {
822 case PDM_SYSCONFIG:
823 case PDM_CTRL0:
824 case PDM_CTRL1:
825 case PDM_CLK_CTRL:
826 case PDM_HPF_CTRL:
827 case PDM_FIFO_CTRL:
828 case PDM_DMA_CTRL:
829 case PDM_INT_EN:
830 case PDM_INT_CLR:
831 case PDM_INT_ST:
832 case PDM_DATA_VALID:
833 case PDM_RXFIFO_DATA:
834 case PDM_VERSION:
835 return true;
836 default:
837 return false;
838 }
839 }
840
rockchip_pdm_volatile_reg(struct device * dev,unsigned int reg)841 static bool rockchip_pdm_volatile_reg(struct device *dev, unsigned int reg)
842 {
843 switch (reg) {
844 case PDM_SYSCONFIG:
845 case PDM_FIFO_CTRL:
846 case PDM_INT_CLR:
847 case PDM_INT_ST:
848 case PDM_RXFIFO_DATA:
849 return true;
850 default:
851 return false;
852 }
853 }
854
rockchip_pdm_precious_reg(struct device * dev,unsigned int reg)855 static bool rockchip_pdm_precious_reg(struct device *dev, unsigned int reg)
856 {
857 switch (reg) {
858 case PDM_RXFIFO_DATA:
859 return true;
860 default:
861 return false;
862 }
863 }
864
865 static const struct reg_default rockchip_pdm_reg_defaults[] = {
866 { PDM_CTRL0, 0x78000017 },
867 { PDM_CTRL1, 0x0bb8ea60 },
868 { PDM_CLK_CTRL, 0x0000e401 },
869 { PDM_DMA_CTRL, 0x0000001f },
870 };
871
872 static const struct regmap_config rockchip_pdm_regmap_config = {
873 .reg_bits = 32,
874 .reg_stride = 4,
875 .val_bits = 32,
876 .max_register = PDM_VERSION,
877 .reg_defaults = rockchip_pdm_reg_defaults,
878 .num_reg_defaults = ARRAY_SIZE(rockchip_pdm_reg_defaults),
879 .writeable_reg = rockchip_pdm_wr_reg,
880 .readable_reg = rockchip_pdm_rd_reg,
881 .volatile_reg = rockchip_pdm_volatile_reg,
882 .precious_reg = rockchip_pdm_precious_reg,
883 .cache_type = REGCACHE_FLAT,
884 };
885
886 static const struct of_device_id rockchip_pdm_match[] __maybe_unused = {
887 { .compatible = "rockchip,pdm",
888 .data = (void *)RK_PDM_RK3229 },
889 { .compatible = "rockchip,px30-pdm",
890 .data = (void *)RK_PDM_RK3308 },
891 { .compatible = "rockchip,rk1808-pdm",
892 .data = (void *)RK_PDM_RK3308 },
893 { .compatible = "rockchip,rk3308-pdm",
894 .data = (void *)RK_PDM_RK3308 },
895 { .compatible = "rockchip,rk3568-pdm",
896 .data = (void *)RK_PDM_RV1126 },
897 { .compatible = "rockchip,rk3588-pdm",
898 .data = (void *)RK_PDM_RK3588 },
899 { .compatible = "rockchip,rv1126-pdm",
900 .data = (void *)RK_PDM_RV1126 },
901 {},
902 };
903 MODULE_DEVICE_TABLE(of, rockchip_pdm_match);
904
rockchip_pdm_path_parse(struct rk_pdm_dev * pdm,struct device_node * node)905 static int rockchip_pdm_path_parse(struct rk_pdm_dev *pdm, struct device_node *node)
906 {
907 unsigned int path[PDM_PATH_MAX];
908 int cnt = 0, ret = 0, i = 0, val = 0, msk = 0;
909
910 cnt = of_count_phandle_with_args(node, "rockchip,path-map",
911 NULL);
912 if (cnt != PDM_PATH_MAX)
913 return cnt;
914
915 ret = of_property_read_u32_array(node, "rockchip,path-map",
916 path, cnt);
917 if (ret)
918 return ret;
919
920 for (i = 0; i < cnt; i++) {
921 if (path[i] >= PDM_PATH_MAX)
922 return -EINVAL;
923 msk |= PDM_PATH_MASK(i);
924 val |= PDM_PATH(i, path[i]);
925 }
926
927 regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, msk, val);
928
929 return 0;
930 }
931
rockchip_pdm_probe(struct platform_device * pdev)932 static int rockchip_pdm_probe(struct platform_device *pdev)
933 {
934 struct device_node *node = pdev->dev.of_node;
935 const struct of_device_id *match;
936 struct rk_pdm_dev *pdm;
937 struct resource *res;
938 void __iomem *regs;
939 int ret;
940
941 pdm = devm_kzalloc(&pdev->dev, sizeof(*pdm), GFP_KERNEL);
942 if (!pdm)
943 return -ENOMEM;
944
945 match = of_match_device(rockchip_pdm_match, &pdev->dev);
946 if (match)
947 pdm->version = (enum rk_pdm_version)match->data;
948
949 if (pdm->version == RK_PDM_RK3308) {
950 pdm->reset = devm_reset_control_get(&pdev->dev, "pdm-m");
951 if (IS_ERR(pdm->reset))
952 return PTR_ERR(pdm->reset);
953 }
954
955 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
956 if (IS_ERR(regs))
957 return PTR_ERR(regs);
958
959 pdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
960 &rockchip_pdm_regmap_config);
961 if (IS_ERR(pdm->regmap))
962 return PTR_ERR(pdm->regmap);
963
964 pdm->capture_dma_data.addr = res->start + PDM_RXFIFO_DATA;
965 pdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
966 pdm->capture_dma_data.maxburst = PDM_DMA_BURST_SIZE;
967
968 pdm->dev = &pdev->dev;
969 dev_set_drvdata(&pdev->dev, pdm);
970
971 pdm->pinctrl = devm_pinctrl_get(&pdev->dev);
972 if (!IS_ERR_OR_NULL(pdm->pinctrl)) {
973 pdm->clk_state = pinctrl_lookup_state(pdm->pinctrl, "clk");
974 if (IS_ERR(pdm->clk_state)) {
975 pdm->clk_state = NULL;
976 dev_dbg(pdm->dev, "Have no clk pinctrl state\n");
977 }
978 }
979
980 pdm->start_delay_ms = PDM_START_DELAY_MS_DEFAULT;
981 pdm->filter_delay_ms = PDM_FILTER_DELAY_MS_MIN;
982
983 pdm->clk_calibrate =
984 of_property_read_bool(node, "rockchip,mclk-calibrate");
985 if (pdm->clk_calibrate) {
986 pdm->clk_root = devm_clk_get(&pdev->dev, "pdm_clk_root");
987 if (IS_ERR(pdm->clk_root))
988 return PTR_ERR(pdm->clk_root);
989
990 pdm->clk_root_initial_rate = clk_get_rate(pdm->clk_root);
991 pdm->clk_root_rate = pdm->clk_root_initial_rate;
992 }
993
994 pdm->clk = devm_clk_get(&pdev->dev, "pdm_clk");
995 if (IS_ERR(pdm->clk))
996 return PTR_ERR(pdm->clk);
997
998 pdm->hclk = devm_clk_get(&pdev->dev, "pdm_hclk");
999 if (IS_ERR(pdm->hclk))
1000 return PTR_ERR(pdm->hclk);
1001
1002 ret = clk_prepare_enable(pdm->hclk);
1003 if (ret)
1004 return ret;
1005
1006 pm_runtime_enable(&pdev->dev);
1007 if (!pm_runtime_enabled(&pdev->dev)) {
1008 ret = rockchip_pdm_runtime_resume(&pdev->dev);
1009 if (ret)
1010 goto err_pm_disable;
1011 }
1012
1013 ret = devm_snd_soc_register_component(&pdev->dev,
1014 &rockchip_pdm_component,
1015 &rockchip_pdm_dai, 1);
1016
1017 if (ret) {
1018 dev_err(&pdev->dev, "could not register dai: %d\n", ret);
1019 goto err_suspend;
1020 }
1021
1022 rockchip_pdm_set_samplerate(pdm, PDM_DEFAULT_RATE);
1023 rockchip_pdm_rxctrl(pdm, 0);
1024
1025 ret = rockchip_pdm_path_parse(pdm, node);
1026 if (ret != 0 && ret != -ENOENT)
1027 goto err_suspend;
1028
1029 if (of_property_read_bool(node, "rockchip,no-dmaengine")) {
1030 dev_info(&pdev->dev, "Used for Multi-DAI\n");
1031 return 0;
1032 }
1033
1034 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1035 if (ret) {
1036 dev_err(&pdev->dev, "could not register pcm: %d\n", ret);
1037 goto err_suspend;
1038 }
1039
1040 clk_disable_unprepare(pdm->hclk);
1041
1042 return 0;
1043
1044 err_suspend:
1045 if (!pm_runtime_status_suspended(&pdev->dev))
1046 rockchip_pdm_runtime_suspend(&pdev->dev);
1047 err_pm_disable:
1048 pm_runtime_disable(&pdev->dev);
1049
1050 clk_disable_unprepare(pdm->hclk);
1051
1052 return ret;
1053 }
1054
rockchip_pdm_remove(struct platform_device * pdev)1055 static int rockchip_pdm_remove(struct platform_device *pdev)
1056 {
1057 pm_runtime_disable(&pdev->dev);
1058 if (!pm_runtime_status_suspended(&pdev->dev))
1059 rockchip_pdm_runtime_suspend(&pdev->dev);
1060
1061 return 0;
1062 }
1063
1064 #ifdef CONFIG_PM_SLEEP
rockchip_pdm_suspend(struct device * dev)1065 static int rockchip_pdm_suspend(struct device *dev)
1066 {
1067 struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
1068
1069 regcache_mark_dirty(pdm->regmap);
1070
1071 return 0;
1072 }
1073
rockchip_pdm_resume(struct device * dev)1074 static int rockchip_pdm_resume(struct device *dev)
1075 {
1076 struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
1077 int ret;
1078
1079 ret = pm_runtime_get_sync(dev);
1080 if (ret < 0) {
1081 pm_runtime_put(dev);
1082 return ret;
1083 }
1084
1085 ret = regcache_sync(pdm->regmap);
1086
1087 pm_runtime_put(dev);
1088
1089 return ret;
1090 }
1091 #endif
1092
1093 static const struct dev_pm_ops rockchip_pdm_pm_ops = {
1094 SET_RUNTIME_PM_OPS(rockchip_pdm_runtime_suspend,
1095 rockchip_pdm_runtime_resume, NULL)
1096 SET_SYSTEM_SLEEP_PM_OPS(rockchip_pdm_suspend, rockchip_pdm_resume)
1097 };
1098
1099 static struct platform_driver rockchip_pdm_driver = {
1100 .probe = rockchip_pdm_probe,
1101 .remove = rockchip_pdm_remove,
1102 .driver = {
1103 .name = "rockchip-pdm",
1104 .of_match_table = of_match_ptr(rockchip_pdm_match),
1105 .pm = &rockchip_pdm_pm_ops,
1106 },
1107 };
1108
1109 module_platform_driver(rockchip_pdm_driver);
1110
1111 MODULE_AUTHOR("Sugar <sugar.zhang@rock-chips.com>");
1112 MODULE_DESCRIPTION("Rockchip PDM Controller Driver");
1113 MODULE_LICENSE("GPL v2");
1114