1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rockchip_i2s.c
3 *
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 *
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
8 */
9
10 #include <linux/module.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/delay.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_device.h>
15 #include <linux/clk.h>
16 #include <linux/clk/rockchip.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <linux/spinlock.h>
20 #include <sound/pcm_params.h>
21 #include <sound/dmaengine_pcm.h>
22
23 #include "rockchip_i2s.h"
24
25 #define DRV_NAME "rockchip-i2s"
26
27 #define CLK_PPM_MIN (-1000)
28 #define CLK_PPM_MAX (1000)
29
30 struct rk_i2s_pins {
31 u32 reg_offset;
32 u32 shift;
33 };
34
35 struct rk_i2s_dev {
36 struct device *dev;
37
38 struct clk *hclk;
39 struct clk *mclk;
40 struct clk *mclk_root;
41
42 struct snd_dmaengine_dai_dma_data capture_dma_data;
43 struct snd_dmaengine_dai_dma_data playback_dma_data;
44
45 struct regmap *regmap;
46 struct regmap *grf;
47
48 bool has_capture;
49 bool has_playback;
50
51 /*
52 * Used to indicate the tx/rx status.
53 * I2S controller hopes to start the tx and rx together,
54 * also to stop them when they are both try to stop.
55 */
56 bool tx_start;
57 bool rx_start;
58 bool is_master_mode;
59 const struct rk_i2s_pins *pins;
60 unsigned int bclk_ratio;
61 spinlock_t lock; /* tx/rx lock */
62 unsigned int clk_trcm;
63
64 unsigned int mclk_root_rate;
65 unsigned int mclk_root_initial_rate;
66 int clk_ppm;
67 bool mclk_calibrate;
68
69 };
70
i2s_runtime_suspend(struct device * dev)71 static int i2s_runtime_suspend(struct device *dev)
72 {
73 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
74
75 regcache_cache_only(i2s->regmap, true);
76 clk_disable_unprepare(i2s->mclk);
77
78 return 0;
79 }
80
i2s_runtime_resume(struct device * dev)81 static int i2s_runtime_resume(struct device *dev)
82 {
83 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
84 int ret;
85
86 ret = clk_prepare_enable(i2s->mclk);
87 if (ret) {
88 dev_err(i2s->dev, "clock enable failed %d\n", ret);
89 return ret;
90 }
91
92 regcache_cache_only(i2s->regmap, false);
93 regcache_mark_dirty(i2s->regmap);
94
95 ret = regcache_sync(i2s->regmap);
96 if (ret)
97 clk_disable_unprepare(i2s->mclk);
98
99 return ret;
100 }
101
to_info(struct snd_soc_dai * dai)102 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
103 {
104 return snd_soc_dai_get_drvdata(dai);
105 }
106
rockchip_i2s_clear(struct rk_i2s_dev * i2s)107 static int rockchip_i2s_clear(struct rk_i2s_dev *i2s)
108 {
109 unsigned int clr = I2S_CLR_TXC | I2S_CLR_RXC;
110 unsigned int val = 0;
111 int ret;
112
113 /*
114 * Workaround for FIFO clear on SLAVE mode:
115 *
116 * A Suggest to do reset hclk domain and then do mclk
117 * domain, especially for SLAVE mode without CLK in.
118 * at last, recovery regmap config.
119 *
120 * B Suggest to switch to MASTER, and then do FIFO clr,
121 * at last, bring back to SLAVE.
122 *
123 * Now we choose plan B here.
124 */
125 if (!i2s->is_master_mode)
126 regmap_update_bits(i2s->regmap, I2S_CKR,
127 I2S_CKR_MSS_MASK, I2S_CKR_MSS_MASTER);
128 regmap_update_bits(i2s->regmap, I2S_CLR, clr, clr);
129
130 ret = regmap_read_poll_timeout_atomic(i2s->regmap, I2S_CLR, val,
131 !(val & clr), 10, 100);
132 if (!i2s->is_master_mode)
133 regmap_update_bits(i2s->regmap, I2S_CKR,
134 I2S_CKR_MSS_MASK, I2S_CKR_MSS_SLAVE);
135 if (ret < 0)
136 dev_warn(i2s->dev, "failed to clear fifo on %s mode\n",
137 i2s->is_master_mode ? "master" : "slave");
138
139 return ret;
140 }
141
rockchip_snd_txctrl(struct rk_i2s_dev * i2s,int on)142 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
143 {
144 spin_lock(&i2s->lock);
145 if (on) {
146 regmap_update_bits(i2s->regmap, I2S_DMACR,
147 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
148
149 regmap_update_bits(i2s->regmap, I2S_XFER,
150 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
151 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
152
153 i2s->tx_start = true;
154 } else {
155 i2s->tx_start = false;
156
157 regmap_update_bits(i2s->regmap, I2S_DMACR,
158 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
159
160 if (!i2s->rx_start) {
161 regmap_update_bits(i2s->regmap, I2S_XFER,
162 I2S_XFER_TXS_START |
163 I2S_XFER_RXS_START,
164 I2S_XFER_TXS_STOP |
165 I2S_XFER_RXS_STOP);
166
167 udelay(150);
168 rockchip_i2s_clear(i2s);
169 }
170 }
171 spin_unlock(&i2s->lock);
172 }
173
rockchip_snd_rxctrl(struct rk_i2s_dev * i2s,int on)174 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
175 {
176 spin_lock(&i2s->lock);
177 if (on) {
178 regmap_update_bits(i2s->regmap, I2S_DMACR,
179 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
180
181 regmap_update_bits(i2s->regmap, I2S_XFER,
182 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
183 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
184
185 i2s->rx_start = true;
186 } else {
187 i2s->rx_start = false;
188
189 regmap_update_bits(i2s->regmap, I2S_DMACR,
190 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
191
192 if (!i2s->tx_start) {
193 regmap_update_bits(i2s->regmap, I2S_XFER,
194 I2S_XFER_TXS_START |
195 I2S_XFER_RXS_START,
196 I2S_XFER_TXS_STOP |
197 I2S_XFER_RXS_STOP);
198
199 udelay(150);
200 rockchip_i2s_clear(i2s);
201 }
202 }
203 spin_unlock(&i2s->lock);
204 }
205
rockchip_i2s_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)206 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
207 unsigned int fmt)
208 {
209 struct rk_i2s_dev *i2s = to_info(cpu_dai);
210 unsigned int mask = 0, val = 0;
211 int ret = 0;
212
213 pm_runtime_get_sync(cpu_dai->dev);
214 mask = I2S_CKR_MSS_MASK;
215 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
216 case SND_SOC_DAIFMT_CBS_CFS:
217 /* Set source clock in Master mode */
218 val = I2S_CKR_MSS_MASTER;
219 i2s->is_master_mode = true;
220 break;
221 case SND_SOC_DAIFMT_CBM_CFM:
222 val = I2S_CKR_MSS_SLAVE;
223 i2s->is_master_mode = false;
224 break;
225 default:
226 ret = -EINVAL;
227 goto err_pm_put;
228 }
229
230 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
231
232 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
233 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
234 case SND_SOC_DAIFMT_NB_NF:
235 val = I2S_CKR_CKP_NORMAL |
236 I2S_CKR_TLP_NORMAL |
237 I2S_CKR_RLP_NORMAL;
238 break;
239 case SND_SOC_DAIFMT_NB_IF:
240 val = I2S_CKR_CKP_NORMAL |
241 I2S_CKR_TLP_INVERTED |
242 I2S_CKR_RLP_INVERTED;
243 break;
244 case SND_SOC_DAIFMT_IB_NF:
245 val = I2S_CKR_CKP_INVERTED |
246 I2S_CKR_TLP_NORMAL |
247 I2S_CKR_RLP_NORMAL;
248 break;
249 case SND_SOC_DAIFMT_IB_IF:
250 val = I2S_CKR_CKP_INVERTED |
251 I2S_CKR_TLP_INVERTED |
252 I2S_CKR_RLP_INVERTED;
253 break;
254 default:
255 ret = -EINVAL;
256 goto err_pm_put;
257 }
258
259 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
260
261 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
262 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
263 case SND_SOC_DAIFMT_RIGHT_J:
264 val = I2S_TXCR_IBM_RSJM;
265 break;
266 case SND_SOC_DAIFMT_LEFT_J:
267 val = I2S_TXCR_IBM_LSJM;
268 break;
269 case SND_SOC_DAIFMT_I2S:
270 val = I2S_TXCR_IBM_NORMAL;
271 break;
272 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
273 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
274 break;
275 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
276 val = I2S_TXCR_TFS_PCM;
277 break;
278 default:
279 ret = -EINVAL;
280 goto err_pm_put;
281 }
282
283 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
284
285 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
286 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
287 case SND_SOC_DAIFMT_RIGHT_J:
288 val = I2S_RXCR_IBM_RSJM;
289 break;
290 case SND_SOC_DAIFMT_LEFT_J:
291 val = I2S_RXCR_IBM_LSJM;
292 break;
293 case SND_SOC_DAIFMT_I2S:
294 val = I2S_RXCR_IBM_NORMAL;
295 break;
296 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
297 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
298 break;
299 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
300 val = I2S_RXCR_TFS_PCM;
301 break;
302 default:
303 ret = -EINVAL;
304 goto err_pm_put;
305 }
306
307 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
308
309 err_pm_put:
310 pm_runtime_put(cpu_dai->dev);
311
312 return ret;
313 }
314
rockchip_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)315 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
316 struct snd_pcm_hw_params *params,
317 struct snd_soc_dai *dai)
318 {
319 struct rk_i2s_dev *i2s = to_info(dai);
320 unsigned int val = 0;
321 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
322
323 if (i2s->is_master_mode) {
324 mclk_rate = clk_get_rate(i2s->mclk);
325 bclk_rate = i2s->bclk_ratio * params_rate(params);
326 if (!bclk_rate)
327 return -EINVAL;
328
329 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
330 div_lrck = bclk_rate / params_rate(params);
331 regmap_update_bits(i2s->regmap, I2S_CKR,
332 I2S_CKR_MDIV_MASK,
333 I2S_CKR_MDIV(div_bclk));
334
335 regmap_update_bits(i2s->regmap, I2S_CKR,
336 I2S_CKR_TSD_MASK |
337 I2S_CKR_RSD_MASK,
338 I2S_CKR_TSD(div_lrck) |
339 I2S_CKR_RSD(div_lrck));
340 }
341
342 switch (params_format(params)) {
343 case SNDRV_PCM_FORMAT_S8:
344 val |= I2S_TXCR_VDW(8);
345 break;
346 case SNDRV_PCM_FORMAT_S16_LE:
347 val |= I2S_TXCR_VDW(16);
348 break;
349 case SNDRV_PCM_FORMAT_S20_3LE:
350 val |= I2S_TXCR_VDW(20);
351 break;
352 case SNDRV_PCM_FORMAT_S24_LE:
353 val |= I2S_TXCR_VDW(24);
354 break;
355 case SNDRV_PCM_FORMAT_S32_LE:
356 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
357 val |= I2S_TXCR_VDW(32);
358 break;
359 default:
360 return -EINVAL;
361 }
362
363 switch (params_channels(params)) {
364 case 8:
365 val |= I2S_CHN_8;
366 break;
367 case 6:
368 val |= I2S_CHN_6;
369 break;
370 case 4:
371 val |= I2S_CHN_4;
372 break;
373 case 2:
374 val |= I2S_CHN_2;
375 break;
376 default:
377 dev_err(i2s->dev, "invalid channel: %d\n",
378 params_channels(params));
379 return -EINVAL;
380 }
381
382 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
383 regmap_update_bits(i2s->regmap, I2S_RXCR,
384 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
385 val);
386 else
387 regmap_update_bits(i2s->regmap, I2S_TXCR,
388 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
389 val);
390
391 if (!IS_ERR(i2s->grf) && i2s->pins) {
392 regmap_read(i2s->regmap, I2S_TXCR, &val);
393 val &= I2S_TXCR_CSR_MASK;
394
395 switch (val) {
396 case I2S_CHN_4:
397 val = I2S_IO_4CH_OUT_6CH_IN;
398 break;
399 case I2S_CHN_6:
400 val = I2S_IO_6CH_OUT_4CH_IN;
401 break;
402 case I2S_CHN_8:
403 val = I2S_IO_8CH_OUT_2CH_IN;
404 break;
405 default:
406 val = I2S_IO_2CH_OUT_8CH_IN;
407 break;
408 }
409
410 val <<= i2s->pins->shift;
411 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
412 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
413 }
414
415 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
416 I2S_DMACR_TDL(16));
417 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
418 I2S_DMACR_RDL(16));
419
420 return 0;
421 }
422
rockchip_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)423 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
424 int cmd, struct snd_soc_dai *dai)
425 {
426 struct rk_i2s_dev *i2s = to_info(dai);
427 int ret = 0;
428
429 switch (cmd) {
430 case SNDRV_PCM_TRIGGER_START:
431 case SNDRV_PCM_TRIGGER_RESUME:
432 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
433 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
434 rockchip_snd_rxctrl(i2s, 1);
435 else
436 rockchip_snd_txctrl(i2s, 1);
437 break;
438 case SNDRV_PCM_TRIGGER_SUSPEND:
439 case SNDRV_PCM_TRIGGER_STOP:
440 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
441 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
442 rockchip_snd_rxctrl(i2s, 0);
443 else
444 rockchip_snd_txctrl(i2s, 0);
445 break;
446 default:
447 ret = -EINVAL;
448 break;
449 }
450
451 return ret;
452 }
453
rockchip_i2s_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)454 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
455 unsigned int ratio)
456 {
457 struct rk_i2s_dev *i2s = to_info(dai);
458
459 i2s->bclk_ratio = ratio;
460
461 return 0;
462 }
463
rockchip_i2s_clk_set_rate(struct rk_i2s_dev * i2s,struct clk * clk,unsigned long rate,int ppm)464 static int rockchip_i2s_clk_set_rate(struct rk_i2s_dev *i2s,
465 struct clk *clk, unsigned long rate,
466 int ppm)
467 {
468 unsigned long rate_target;
469 int delta, ret;
470
471 if (ppm == i2s->clk_ppm)
472 return 0;
473
474 ret = rockchip_pll_clk_compensation(clk, ppm);
475 if (ret != -ENOSYS)
476 goto out;
477
478 delta = (ppm < 0) ? -1 : 1;
479 delta *= (int)div64_u64((uint64_t)rate * (uint64_t)abs(ppm) + 500000, 1000000);
480
481 rate_target = rate + delta;
482
483 if (!rate_target)
484 return -EINVAL;
485
486 ret = clk_set_rate(clk, rate_target);
487 if (ret)
488 return ret;
489 out:
490 if (!ret)
491 i2s->clk_ppm = ppm;
492
493 return ret;
494 }
495
rockchip_i2s_set_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int rate,int dir)496 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
497 unsigned int rate, int dir)
498 {
499 struct rk_i2s_dev *i2s = to_info(cpu_dai);
500 unsigned int root_rate, div, delta;
501 uint64_t ppm;
502 int ret;
503
504 if (rate == 0)
505 return 0;
506
507 if (i2s->mclk_calibrate) {
508 ret = rockchip_i2s_clk_set_rate(i2s, i2s->mclk_root,
509 i2s->mclk_root_rate, 0);
510 if (ret)
511 return ret;
512
513 root_rate = i2s->mclk_root_rate;
514 delta = abs(root_rate % rate - rate);
515 ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)root_rate);
516
517 if (ppm) {
518 div = DIV_ROUND_CLOSEST(i2s->mclk_root_initial_rate, rate);
519 if (!div)
520 return -EINVAL;
521
522 root_rate = rate * round_up(div, 2);
523 ret = clk_set_rate(i2s->mclk_root, root_rate);
524 if (ret)
525 return ret;
526
527 i2s->mclk_root_rate = clk_get_rate(i2s->mclk_root);
528 }
529 }
530
531 ret = clk_set_rate(i2s->mclk, rate);
532 if (ret)
533 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
534
535 return ret;
536 }
537
rockchip_i2s_clk_compensation_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)538 static int rockchip_i2s_clk_compensation_info(struct snd_kcontrol *kcontrol,
539 struct snd_ctl_elem_info *uinfo)
540 {
541 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
542 uinfo->count = 1;
543 uinfo->value.integer.min = CLK_PPM_MIN;
544 uinfo->value.integer.max = CLK_PPM_MAX;
545 uinfo->value.integer.step = 1;
546
547 return 0;
548 }
549
rockchip_i2s_clk_compensation_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)550 static int rockchip_i2s_clk_compensation_get(struct snd_kcontrol *kcontrol,
551 struct snd_ctl_elem_value *ucontrol)
552 {
553 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
554 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
555
556 ucontrol->value.integer.value[0] = i2s->clk_ppm;
557
558 return 0;
559 }
560
rockchip_i2s_clk_compensation_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)561 static int rockchip_i2s_clk_compensation_put(struct snd_kcontrol *kcontrol,
562 struct snd_ctl_elem_value *ucontrol)
563 {
564 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
565 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
566 int ppm = ucontrol->value.integer.value[0];
567
568 if ((ucontrol->value.integer.value[0] < CLK_PPM_MIN) ||
569 (ucontrol->value.integer.value[0] > CLK_PPM_MAX))
570 return -EINVAL;
571
572 return rockchip_i2s_clk_set_rate(i2s, i2s->mclk_root, i2s->mclk_root_rate, ppm);
573 }
574
575 static struct snd_kcontrol_new rockchip_i2s_compensation_control = {
576 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
577 .name = "PCM Clk Compensation In PPM",
578 .info = rockchip_i2s_clk_compensation_info,
579 .get = rockchip_i2s_clk_compensation_get,
580 .put = rockchip_i2s_clk_compensation_put,
581 };
582
rockchip_i2s_dai_probe(struct snd_soc_dai * dai)583 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
584 {
585 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
586
587 snd_soc_dai_init_dma_data(dai,
588 i2s->has_playback ? &i2s->playback_dma_data : NULL,
589 i2s->has_capture ? &i2s->capture_dma_data : NULL);
590
591 if (i2s->mclk_calibrate)
592 snd_soc_add_dai_controls(dai, &rockchip_i2s_compensation_control, 1);
593
594 return 0;
595 }
596
597 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
598 .hw_params = rockchip_i2s_hw_params,
599 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
600 .set_sysclk = rockchip_i2s_set_sysclk,
601 .set_fmt = rockchip_i2s_set_fmt,
602 .trigger = rockchip_i2s_trigger,
603 };
604
605 static struct snd_soc_dai_driver rockchip_i2s_dai = {
606 .probe = rockchip_i2s_dai_probe,
607 .ops = &rockchip_i2s_dai_ops,
608 };
609
610 static const struct snd_soc_component_driver rockchip_i2s_component = {
611 .name = DRV_NAME,
612 };
613
rockchip_i2s_wr_reg(struct device * dev,unsigned int reg)614 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
615 {
616 switch (reg) {
617 case I2S_TXCR:
618 case I2S_RXCR:
619 case I2S_CKR:
620 case I2S_DMACR:
621 case I2S_INTCR:
622 case I2S_XFER:
623 case I2S_CLR:
624 case I2S_TXDR:
625 return true;
626 default:
627 return false;
628 }
629 }
630
rockchip_i2s_rd_reg(struct device * dev,unsigned int reg)631 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
632 {
633 switch (reg) {
634 case I2S_TXCR:
635 case I2S_RXCR:
636 case I2S_CKR:
637 case I2S_DMACR:
638 case I2S_INTCR:
639 case I2S_XFER:
640 case I2S_CLR:
641 case I2S_TXDR:
642 case I2S_RXDR:
643 case I2S_FIFOLR:
644 case I2S_INTSR:
645 return true;
646 default:
647 return false;
648 }
649 }
650
rockchip_i2s_volatile_reg(struct device * dev,unsigned int reg)651 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
652 {
653 switch (reg) {
654 case I2S_INTSR:
655 case I2S_CLR:
656 case I2S_FIFOLR:
657 case I2S_TXDR:
658 case I2S_RXDR:
659 return true;
660 default:
661 return false;
662 }
663 }
664
rockchip_i2s_precious_reg(struct device * dev,unsigned int reg)665 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
666 {
667 switch (reg) {
668 case I2S_RXDR:
669 return true;
670 default:
671 return false;
672 }
673 }
674
675 static const struct reg_default rockchip_i2s_reg_defaults[] = {
676 {0x00, 0x0000000f},
677 {0x04, 0x0000000f},
678 {0x08, 0x00071f1f},
679 {0x10, 0x001f0000},
680 {0x14, 0x01f00000},
681 };
682
683 static const struct regmap_config rockchip_i2s_regmap_config = {
684 .reg_bits = 32,
685 .reg_stride = 4,
686 .val_bits = 32,
687 .max_register = I2S_RXDR,
688 .reg_defaults = rockchip_i2s_reg_defaults,
689 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
690 .writeable_reg = rockchip_i2s_wr_reg,
691 .readable_reg = rockchip_i2s_rd_reg,
692 .volatile_reg = rockchip_i2s_volatile_reg,
693 .precious_reg = rockchip_i2s_precious_reg,
694 .cache_type = REGCACHE_FLAT,
695 };
696
697 static const struct rk_i2s_pins rk3399_i2s_pins = {
698 .reg_offset = 0xe220,
699 .shift = 11,
700 };
701
702 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
703 #ifdef CONFIG_CPU_PX30
704 { .compatible = "rockchip,px30-i2s", },
705 #endif
706 #ifdef CONFIG_CPU_RK1808
707 { .compatible = "rockchip,rk1808-i2s", },
708 #endif
709 #ifdef CONFIG_CPU_RK3036
710 { .compatible = "rockchip,rk3036-i2s", },
711 #endif
712 { .compatible = "rockchip,rk3066-i2s", },
713 #ifdef CONFIG_CPU_RK312X
714 { .compatible = "rockchip,rk3128-i2s", },
715 #endif
716 #ifdef CONFIG_CPU_RK3188
717 { .compatible = "rockchip,rk3188-i2s", },
718 #endif
719 #ifdef CONFIG_CPU_RK322X
720 { .compatible = "rockchip,rk3228-i2s", },
721 #endif
722 #ifdef CONFIG_CPU_RK3288
723 { .compatible = "rockchip,rk3288-i2s", },
724 #endif
725 #ifdef CONFIG_CPU_RK3308
726 { .compatible = "rockchip,rk3308-i2s", },
727 #endif
728 #ifdef CONFIG_CPU_RK3328
729 { .compatible = "rockchip,rk3328-i2s", },
730 #endif
731 #ifdef CONFIG_CPU_RK3366
732 { .compatible = "rockchip,rk3366-i2s", },
733 #endif
734 #ifdef CONFIG_CPU_RK3368
735 { .compatible = "rockchip,rk3368-i2s", },
736 #endif
737 #ifdef CONFIG_CPU_RK3399
738 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
739 #endif
740 #ifdef CONFIG_CPU_RV1126
741 { .compatible = "rockchip,rv1126-i2s", },
742 #endif
743 {},
744 };
745
rockchip_i2s_init_dai(struct rk_i2s_dev * i2s,struct resource * res,struct snd_soc_dai_driver ** dp)746 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
747 struct snd_soc_dai_driver **dp)
748 {
749 struct device_node *node = i2s->dev->of_node;
750 struct snd_soc_dai_driver *dai;
751 struct property *dma_names;
752 const char *dma_name;
753 unsigned int val;
754
755 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
756 if (!strcmp(dma_name, "tx"))
757 i2s->has_playback = true;
758 if (!strcmp(dma_name, "rx"))
759 i2s->has_capture = true;
760 }
761
762 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
763 sizeof(*dai), GFP_KERNEL);
764 if (!dai)
765 return -ENOMEM;
766
767 if (i2s->has_playback) {
768 dai->playback.stream_name = "Playback";
769 dai->playback.channels_min = 2;
770 dai->playback.channels_max = 8;
771 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
772 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
773 SNDRV_PCM_FMTBIT_S16_LE |
774 SNDRV_PCM_FMTBIT_S20_3LE |
775 SNDRV_PCM_FMTBIT_S24_LE |
776 SNDRV_PCM_FMTBIT_S32_LE |
777 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
778
779 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
780 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
781 i2s->playback_dma_data.maxburst = 8;
782
783 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
784 if (val >= 2 && val <= 8)
785 dai->playback.channels_max = val;
786 }
787 }
788
789 if (i2s->has_capture) {
790 dai->capture.stream_name = "Capture";
791 dai->capture.channels_min = 2;
792 dai->capture.channels_max = 8;
793 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
794 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
795 SNDRV_PCM_FMTBIT_S16_LE |
796 SNDRV_PCM_FMTBIT_S20_3LE |
797 SNDRV_PCM_FMTBIT_S24_LE |
798 SNDRV_PCM_FMTBIT_S32_LE |
799 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
800
801 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
802 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
803 i2s->capture_dma_data.maxburst = 8;
804
805 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
806 if (val >= 2 && val <= 8)
807 dai->capture.channels_max = val;
808 }
809 }
810
811 i2s->clk_trcm = I2S_CKR_TRCM_TXRX;
812 if (!of_property_read_u32(node, "rockchip,clk-trcm", &val)) {
813 if (val >= 0 && val <= 2) {
814 i2s->clk_trcm = val << I2S_CKR_TRCM_SHIFT;
815 if (i2s->clk_trcm)
816 dai->symmetric_rates = 1;
817 }
818 }
819
820 regmap_update_bits(i2s->regmap, I2S_CKR,
821 I2S_CKR_TRCM_MASK, i2s->clk_trcm);
822
823 if (dp)
824 *dp = dai;
825
826 return 0;
827 }
828
rockchip_i2s_probe(struct platform_device * pdev)829 static int rockchip_i2s_probe(struct platform_device *pdev)
830 {
831 struct device_node *node = pdev->dev.of_node;
832 const struct of_device_id *of_id;
833 struct rk_i2s_dev *i2s;
834 struct snd_soc_dai_driver *dai;
835 struct resource *res;
836 void __iomem *regs;
837 int ret;
838
839 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
840 if (!i2s)
841 return -ENOMEM;
842
843 spin_lock_init(&i2s->lock);
844 i2s->dev = &pdev->dev;
845
846 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
847 if (!IS_ERR(i2s->grf)) {
848 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
849 if (!of_id || !of_id->data)
850 return -EINVAL;
851
852 i2s->pins = of_id->data;
853 }
854
855 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
856 if (IS_ERR(regs))
857 return PTR_ERR(regs);
858
859 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
860 &rockchip_i2s_regmap_config);
861 if (IS_ERR(i2s->regmap)) {
862 dev_err(&pdev->dev,
863 "Failed to initialise managed register map\n");
864 return PTR_ERR(i2s->regmap);
865 }
866
867 i2s->bclk_ratio = 64;
868
869 dev_set_drvdata(&pdev->dev, i2s);
870
871 i2s->mclk_calibrate =
872 of_property_read_bool(node, "rockchip,mclk-calibrate");
873 if (i2s->mclk_calibrate) {
874 i2s->mclk_root = devm_clk_get(&pdev->dev, "i2s_clk_root");
875 if (IS_ERR(i2s->mclk_root))
876 return PTR_ERR(i2s->mclk_root);
877
878 i2s->mclk_root_initial_rate = clk_get_rate(i2s->mclk_root);
879 i2s->mclk_root_rate = i2s->mclk_root_initial_rate;
880 }
881
882 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
883 if (IS_ERR(i2s->mclk)) {
884 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
885 return PTR_ERR(i2s->mclk);
886 }
887
888 /* try to prepare related clocks */
889 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
890 if (IS_ERR(i2s->hclk)) {
891 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
892 return PTR_ERR(i2s->hclk);
893 }
894 ret = clk_prepare_enable(i2s->hclk);
895 if (ret) {
896 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
897 return ret;
898 }
899
900 pm_runtime_enable(&pdev->dev);
901 if (!pm_runtime_enabled(&pdev->dev)) {
902 ret = i2s_runtime_resume(&pdev->dev);
903 if (ret)
904 goto err_pm_disable;
905 }
906
907 ret = rockchip_i2s_init_dai(i2s, res, &dai);
908 if (ret)
909 goto err_pm_disable;
910
911 ret = devm_snd_soc_register_component(&pdev->dev,
912 &rockchip_i2s_component,
913 dai, 1);
914
915 if (ret) {
916 dev_err(&pdev->dev, "Could not register DAI\n");
917 goto err_suspend;
918 }
919
920 if (of_property_read_bool(node, "rockchip,no-dmaengine")) {
921 dev_info(&pdev->dev, "Used for Multi-DAI\n");
922 return 0;
923 }
924
925 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
926 if (ret) {
927 dev_err(&pdev->dev, "Could not register PCM\n");
928 goto err_suspend;
929 }
930
931 return 0;
932
933 err_suspend:
934 if (!pm_runtime_status_suspended(&pdev->dev))
935 i2s_runtime_suspend(&pdev->dev);
936 err_pm_disable:
937 pm_runtime_disable(&pdev->dev);
938
939 clk_disable_unprepare(i2s->hclk);
940
941 return ret;
942 }
943
rockchip_i2s_remove(struct platform_device * pdev)944 static int rockchip_i2s_remove(struct platform_device *pdev)
945 {
946 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
947
948 pm_runtime_disable(&pdev->dev);
949 if (!pm_runtime_status_suspended(&pdev->dev))
950 i2s_runtime_suspend(&pdev->dev);
951
952 clk_disable_unprepare(i2s->hclk);
953
954 return 0;
955 }
956
957 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
958 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
959 NULL)
960 };
961
962 static struct platform_driver rockchip_i2s_driver = {
963 .probe = rockchip_i2s_probe,
964 .remove = rockchip_i2s_remove,
965 .driver = {
966 .name = DRV_NAME,
967 .of_match_table = of_match_ptr(rockchip_i2s_match),
968 .pm = &rockchip_i2s_pm_ops,
969 },
970 };
971 module_platform_driver(rockchip_i2s_driver);
972
973 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
974 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
975 MODULE_LICENSE("GPL v2");
976 MODULE_ALIAS("platform:" DRV_NAME);
977 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
978