1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * lpass_hdmi.h - Definitions for the QTi LPASS HDMI 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __LPASS_HDMI_H__ 9*4882a593Smuzhiyun #define __LPASS_HDMI_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/regmap.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define LPASS_HDMITX_LEGACY_DISABLE 0x0 14*4882a593Smuzhiyun #define LPASS_HDMITX_LEGACY_ENABLE 0x1 15*4882a593Smuzhiyun #define LPASS_DP_AUDIO_BITWIDTH16 0x0 16*4882a593Smuzhiyun #define LPASS_DP_AUDIO_BITWIDTH24 0xb 17*4882a593Smuzhiyun #define LPASS_DATA_FORMAT_SHIFT 0x1 18*4882a593Smuzhiyun #define LPASS_FREQ_BIT_SHIFT 24 19*4882a593Smuzhiyun #define LPASS_DATA_FORMAT_LINEAR 0x0 20*4882a593Smuzhiyun #define LPASS_DATA_FORMAT_NON_LINEAR 0x1 21*4882a593Smuzhiyun #define LPASS_SAMPLING_FREQ32 0x3 22*4882a593Smuzhiyun #define LPASS_SAMPLING_FREQ44 0x0 23*4882a593Smuzhiyun #define LPASS_SAMPLING_FREQ48 0x2 24*4882a593Smuzhiyun #define LPASS_TX_CTL_RESET 0x1 25*4882a593Smuzhiyun #define LPASS_TX_CTL_CLEAR 0x0 26*4882a593Smuzhiyun #define LPASS_SSTREAM_ENABLE 1 27*4882a593Smuzhiyun #define LPASS_SSTREAM_DISABLE 0 28*4882a593Smuzhiyun #define LPASS_LAYOUT_SP_DEFAULT 0xf 29*4882a593Smuzhiyun #define LPASS_SSTREAM_DEFAULT_ENABLE 1 30*4882a593Smuzhiyun #define LPASS_SSTREAM_DEFAULT_DISABLE 0 31*4882a593Smuzhiyun #define LPASS_MUTE_ENABLE 1 32*4882a593Smuzhiyun #define LPASS_MUTE_DISABLE 0 33*4882a593Smuzhiyun #define LPASS_META_DEFAULT_VAL 0 34*4882a593Smuzhiyun #define HW_MODE 1 35*4882a593Smuzhiyun #define SW_MODE 0 36*4882a593Smuzhiyun #define LEGACY_LPASS_LPAIF 1 37*4882a593Smuzhiyun #define LEGACY_LPASS_HDMI 0 38*4882a593Smuzhiyun #define REPLACE_VBIT 0x1 39*4882a593Smuzhiyun #define LINEAR_PCM_DATA 0x0 40*4882a593Smuzhiyun #define NON_LINEAR_PCM_DATA 0x1 41*4882a593Smuzhiyun #define HDMITX_PARITY_CALC_EN 0x1 42*4882a593Smuzhiyun #define HDMITX_PARITY_CALC_DIS 0x0 43*4882a593Smuzhiyun #define LPASS_DATA_FORMAT_MASK GENMASK(1, 1) 44*4882a593Smuzhiyun #define LPASS_WORDLENGTH_MASK GENMASK(3, 0) 45*4882a593Smuzhiyun #define LPASS_FREQ_BIT_MASK GENMASK(27, 24) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define LPASS_HDMI_TX_CTL_ADDR(v) (v->hdmi_tx_ctl_addr) 48*4882a593Smuzhiyun #define LPASS_HDMI_TX_LEGACY_ADDR(v) (v->hdmi_legacy_addr) 49*4882a593Smuzhiyun #define LPASS_HDMI_TX_VBIT_CTL_ADDR(v) (v->hdmi_vbit_addr) 50*4882a593Smuzhiyun #define LPASS_HDMI_TX_PARITY_ADDR(v) (v->hdmi_parity_addr) 51*4882a593Smuzhiyun #define LPASS_HDMI_TX_DP_ADDR(v) (v->hdmi_DP_addr) 52*4882a593Smuzhiyun #define LPASS_HDMI_TX_SSTREAM_ADDR(v) (v->hdmi_sstream_addr) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define LPASS_HDMI_TX_CH_LSB_ADDR(v, port) \ 55*4882a593Smuzhiyun (v->hdmi_ch_lsb_addr + v->ch_stride * (port)) 56*4882a593Smuzhiyun #define LPASS_HDMI_TX_CH_MSB_ADDR(v, port) \ 57*4882a593Smuzhiyun (v->hdmi_ch_msb_addr + v->ch_stride * (port)) 58*4882a593Smuzhiyun #define LPASS_HDMI_TX_DMA_ADDR(v, port) \ 59*4882a593Smuzhiyun (v->hdmi_dmactl_addr + v->hdmi_dma_stride * (port)) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct lpass_sstream_ctl { 62*4882a593Smuzhiyun struct regmap_field *sstream_en; 63*4882a593Smuzhiyun struct regmap_field *dma_sel; 64*4882a593Smuzhiyun struct regmap_field *auto_bbit_en; 65*4882a593Smuzhiyun struct regmap_field *layout; 66*4882a593Smuzhiyun struct regmap_field *layout_sp; 67*4882a593Smuzhiyun struct regmap_field *set_sp_on_en; 68*4882a593Smuzhiyun struct regmap_field *dp_audio; 69*4882a593Smuzhiyun struct regmap_field *dp_staffing_en; 70*4882a593Smuzhiyun struct regmap_field *dp_sp_b_hw_en; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct lpass_dp_metadata_ctl { 74*4882a593Smuzhiyun struct regmap_field *mute; 75*4882a593Smuzhiyun struct regmap_field *as_sdp_cc; 76*4882a593Smuzhiyun struct regmap_field *as_sdp_ct; 77*4882a593Smuzhiyun struct regmap_field *aif_db4; 78*4882a593Smuzhiyun struct regmap_field *frequency; 79*4882a593Smuzhiyun struct regmap_field *mst_index; 80*4882a593Smuzhiyun struct regmap_field *dptx_index; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun struct lpass_hdmi_tx_ctl { 84*4882a593Smuzhiyun struct regmap_field *soft_reset; 85*4882a593Smuzhiyun struct regmap_field *force_reset; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct lpass_hdmitx_dmactl { 89*4882a593Smuzhiyun struct regmap_field *use_hw_chs; 90*4882a593Smuzhiyun struct regmap_field *use_hw_usr; 91*4882a593Smuzhiyun struct regmap_field *hw_chs_sel; 92*4882a593Smuzhiyun struct regmap_field *hw_usr_sel; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct lpass_vbit_ctrl { 96*4882a593Smuzhiyun struct regmap_field *replace_vbit; 97*4882a593Smuzhiyun struct regmap_field *vbit_stream; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun extern const struct snd_soc_dai_ops asoc_qcom_lpass_hdmi_dai_ops; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif /* __LPASS_HDMI_H__ */ 103