1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ASoC PXA SSP port support 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _PXA_SSP_H 7*4882a593Smuzhiyun #define _PXA_SSP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* SSP clock sources */ 10*4882a593Smuzhiyun #define PXA_SSP_CLK_PLL 0 11*4882a593Smuzhiyun #define PXA_SSP_CLK_EXT 1 12*4882a593Smuzhiyun #define PXA_SSP_CLK_NET 2 13*4882a593Smuzhiyun #define PXA_SSP_CLK_AUDIO 3 14*4882a593Smuzhiyun #define PXA_SSP_CLK_NET_PLL 4 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* SSP audio dividers */ 17*4882a593Smuzhiyun #define PXA_SSP_AUDIO_DIV_ACDS 0 18*4882a593Smuzhiyun #define PXA_SSP_AUDIO_DIV_SCDB 1 19*4882a593Smuzhiyun #define PXA_SSP_DIV_SCR 2 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* SSP ACDS audio dividers values */ 22*4882a593Smuzhiyun #define PXA_SSP_CLK_AUDIO_DIV_1 0 23*4882a593Smuzhiyun #define PXA_SSP_CLK_AUDIO_DIV_2 1 24*4882a593Smuzhiyun #define PXA_SSP_CLK_AUDIO_DIV_4 2 25*4882a593Smuzhiyun #define PXA_SSP_CLK_AUDIO_DIV_8 3 26*4882a593Smuzhiyun #define PXA_SSP_CLK_AUDIO_DIV_16 4 27*4882a593Smuzhiyun #define PXA_SSP_CLK_AUDIO_DIV_32 5 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* SSP divider bypass */ 30*4882a593Smuzhiyun #define PXA_SSP_CLK_SCDB_4 0 31*4882a593Smuzhiyun #define PXA_SSP_CLK_SCDB_1 1 32*4882a593Smuzhiyun #define PXA_SSP_CLK_SCDB_8 2 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define PXA_SSP_PLL_OUT 0 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif 37