1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/sound/soc/pxa/mmp-sspa.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Marvell International Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _MMP_SSPA_H 8*4882a593Smuzhiyun #define _MMP_SSPA_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * SSPA Registers 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #define SSPA_D (0x00) 14*4882a593Smuzhiyun #define SSPA_ID (0x04) 15*4882a593Smuzhiyun #define SSPA_CTL (0x08) 16*4882a593Smuzhiyun #define SSPA_SP (0x0c) 17*4882a593Smuzhiyun #define SSPA_FIFO_UL (0x10) 18*4882a593Smuzhiyun #define SSPA_INT_MASK (0x14) 19*4882a593Smuzhiyun #define SSPA_C (0x18) 20*4882a593Smuzhiyun #define SSPA_FIFO_NOFS (0x1c) 21*4882a593Smuzhiyun #define SSPA_FIFO_SIZE (0x20) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* SSPA Control Register */ 24*4882a593Smuzhiyun #define SSPA_CTL_XPH (1 << 31) /* Read Phase */ 25*4882a593Smuzhiyun #define SSPA_CTL_XFIG (1 << 15) /* Transmit Zeros when FIFO Empty */ 26*4882a593Smuzhiyun #define SSPA_CTL_JST (1 << 3) /* Audio Sample Justification */ 27*4882a593Smuzhiyun #define SSPA_CTL_XFRLEN2_MASK (7 << 24) 28*4882a593Smuzhiyun #define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */ 29*4882a593Smuzhiyun #define SSPA_CTL_XWDLEN2_MASK (7 << 21) 30*4882a593Smuzhiyun #define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */ 31*4882a593Smuzhiyun #define SSPA_CTL_XDATDLY(x) ((x) << 19) /* Transmit Data Delay */ 32*4882a593Smuzhiyun #define SSPA_CTL_XSSZ2_MASK (7 << 16) 33*4882a593Smuzhiyun #define SSPA_CTL_XSSZ2(x) ((x) << 16) /* Transmit Sample Audio Size */ 34*4882a593Smuzhiyun #define SSPA_CTL_XFRLEN1_MASK (7 << 8) 35*4882a593Smuzhiyun #define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */ 36*4882a593Smuzhiyun #define SSPA_CTL_XWDLEN1_MASK (7 << 5) 37*4882a593Smuzhiyun #define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */ 38*4882a593Smuzhiyun #define SSPA_CTL_XSSZ1_MASK (7 << 0) 39*4882a593Smuzhiyun #define SSPA_CTL_XSSZ1(x) ((x) << 0) /* XSSZ1 */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define SSPA_CTL_8_BITS (0x0) /* Sample Size */ 42*4882a593Smuzhiyun #define SSPA_CTL_12_BITS (0x1) 43*4882a593Smuzhiyun #define SSPA_CTL_16_BITS (0x2) 44*4882a593Smuzhiyun #define SSPA_CTL_20_BITS (0x3) 45*4882a593Smuzhiyun #define SSPA_CTL_24_BITS (0x4) 46*4882a593Smuzhiyun #define SSPA_CTL_32_BITS (0x5) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* SSPA Serial Port Register */ 49*4882a593Smuzhiyun #define SSPA_SP_WEN (1 << 31) /* Write Configuration Enable */ 50*4882a593Smuzhiyun #define SSPA_SP_MSL (1 << 18) /* Master Slave Configuration */ 51*4882a593Smuzhiyun #define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */ 52*4882a593Smuzhiyun #define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */ 53*4882a593Smuzhiyun #define SSPA_SP_FFLUSH (1 << 2) /* FIFO Flush */ 54*4882a593Smuzhiyun #define SSPA_SP_S_RST (1 << 1) /* Active High Reset Signal */ 55*4882a593Smuzhiyun #define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */ 56*4882a593Smuzhiyun #define SSPA_SP_FWID_MASK (0x3f << 20) 57*4882a593Smuzhiyun #define SSPA_SP_FWID(x) ((x) << 20) /* Frame-Sync Width */ 58*4882a593Smuzhiyun #define SSPA_TXSP_FPER_MASK (0x3f << 4) 59*4882a593Smuzhiyun #define SSPA_TXSP_FPER(x) ((x) << 4) /* Frame-Sync Active */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* sspa clock sources */ 62*4882a593Smuzhiyun #define MMP_SSPA_CLK_PLL 0 63*4882a593Smuzhiyun #define MMP_SSPA_CLK_VCXO 1 64*4882a593Smuzhiyun #define MMP_SSPA_CLK_AUDIO 3 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* sspa pll id */ 67*4882a593Smuzhiyun #define MMP_SYSCLK 0 68*4882a593Smuzhiyun #define MMP_SSPA_CLK 1 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* _MMP_SSPA_H */ 71