xref: /OK3568_Linux_fs/kernel/sound/soc/pxa/mmp-sspa.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * linux/sound/soc/pxa/mmp-sspa.c
4*4882a593Smuzhiyun  * Base on pxa2xx-ssp.c
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2011 Marvell International Ltd.
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/clk.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/dmaengine.h>
16*4882a593Smuzhiyun #include <linux/pm_runtime.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <sound/core.h>
19*4882a593Smuzhiyun #include <sound/pcm.h>
20*4882a593Smuzhiyun #include <sound/initval.h>
21*4882a593Smuzhiyun #include <sound/pcm_params.h>
22*4882a593Smuzhiyun #include <sound/soc.h>
23*4882a593Smuzhiyun #include <sound/pxa2xx-lib.h>
24*4882a593Smuzhiyun #include <sound/dmaengine_pcm.h>
25*4882a593Smuzhiyun #include "mmp-sspa.h"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun  * SSPA audio private data
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun struct sspa_priv {
31*4882a593Smuzhiyun 	void __iomem *tx_base;
32*4882a593Smuzhiyun 	void __iomem *rx_base;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	struct snd_dmaengine_dai_dma_data playback_dma_data;
35*4882a593Smuzhiyun 	struct snd_dmaengine_dai_dma_data capture_dma_data;
36*4882a593Smuzhiyun 	struct clk *clk;
37*4882a593Smuzhiyun 	struct clk *audio_clk;
38*4882a593Smuzhiyun 	struct clk *sysclk;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	int running_cnt;
41*4882a593Smuzhiyun 	u32 sp;
42*4882a593Smuzhiyun 	u32 ctrl;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
mmp_sspa_tx_enable(struct sspa_priv * sspa)45*4882a593Smuzhiyun static void mmp_sspa_tx_enable(struct sspa_priv *sspa)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	unsigned int sspa_sp = sspa->sp;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	sspa_sp &= ~SSPA_SP_MSL;
50*4882a593Smuzhiyun 	sspa_sp |= SSPA_SP_S_EN;
51*4882a593Smuzhiyun 	sspa_sp |= SSPA_SP_WEN;
52*4882a593Smuzhiyun 	__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
mmp_sspa_tx_disable(struct sspa_priv * sspa)55*4882a593Smuzhiyun static void mmp_sspa_tx_disable(struct sspa_priv *sspa)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	unsigned int sspa_sp = sspa->sp;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	sspa_sp &= ~SSPA_SP_MSL;
60*4882a593Smuzhiyun 	sspa_sp &= ~SSPA_SP_S_EN;
61*4882a593Smuzhiyun 	sspa_sp |= SSPA_SP_WEN;
62*4882a593Smuzhiyun 	__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
mmp_sspa_rx_enable(struct sspa_priv * sspa)65*4882a593Smuzhiyun static void mmp_sspa_rx_enable(struct sspa_priv *sspa)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	unsigned int sspa_sp = sspa->sp;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	sspa_sp |= SSPA_SP_S_EN;
70*4882a593Smuzhiyun 	sspa_sp |= SSPA_SP_WEN;
71*4882a593Smuzhiyun 	__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
mmp_sspa_rx_disable(struct sspa_priv * sspa)74*4882a593Smuzhiyun static void mmp_sspa_rx_disable(struct sspa_priv *sspa)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	unsigned int sspa_sp = sspa->sp;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	sspa_sp &= ~SSPA_SP_S_EN;
79*4882a593Smuzhiyun 	sspa_sp |= SSPA_SP_WEN;
80*4882a593Smuzhiyun 	__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
mmp_sspa_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)83*4882a593Smuzhiyun static int mmp_sspa_startup(struct snd_pcm_substream *substream,
84*4882a593Smuzhiyun 	struct snd_soc_dai *dai)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	clk_prepare_enable(sspa->sysclk);
89*4882a593Smuzhiyun 	clk_prepare_enable(sspa->clk);
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun 
mmp_sspa_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)94*4882a593Smuzhiyun static void mmp_sspa_shutdown(struct snd_pcm_substream *substream,
95*4882a593Smuzhiyun 	struct snd_soc_dai *dai)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	clk_disable_unprepare(sspa->clk);
100*4882a593Smuzhiyun 	clk_disable_unprepare(sspa->sysclk);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun  * Set the SSP ports SYSCLK.
105*4882a593Smuzhiyun  */
mmp_sspa_set_dai_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)106*4882a593Smuzhiyun static int mmp_sspa_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
107*4882a593Smuzhiyun 				    int clk_id, unsigned int freq, int dir)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
110*4882a593Smuzhiyun 	struct device *dev = cpu_dai->component->dev;
111*4882a593Smuzhiyun 	int ret = 0;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	if (dev->of_node)
114*4882a593Smuzhiyun 		return -ENOTSUPP;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	switch (clk_id) {
117*4882a593Smuzhiyun 	case MMP_SSPA_CLK_AUDIO:
118*4882a593Smuzhiyun 		ret = clk_set_rate(sspa->audio_clk, freq);
119*4882a593Smuzhiyun 		if (ret)
120*4882a593Smuzhiyun 			return ret;
121*4882a593Smuzhiyun 		break;
122*4882a593Smuzhiyun 	case MMP_SSPA_CLK_PLL:
123*4882a593Smuzhiyun 	case MMP_SSPA_CLK_VCXO:
124*4882a593Smuzhiyun 		/* not support yet */
125*4882a593Smuzhiyun 		return -EINVAL;
126*4882a593Smuzhiyun 	default:
127*4882a593Smuzhiyun 		return -EINVAL;
128*4882a593Smuzhiyun 	}
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
mmp_sspa_set_dai_pll(struct snd_soc_dai * cpu_dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)133*4882a593Smuzhiyun static int mmp_sspa_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
134*4882a593Smuzhiyun 				 int source, unsigned int freq_in,
135*4882a593Smuzhiyun 				 unsigned int freq_out)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
138*4882a593Smuzhiyun 	struct device *dev = cpu_dai->component->dev;
139*4882a593Smuzhiyun 	int ret = 0;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	if (dev->of_node)
142*4882a593Smuzhiyun 		return -ENOTSUPP;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	switch (pll_id) {
145*4882a593Smuzhiyun 	case MMP_SYSCLK:
146*4882a593Smuzhiyun 		ret = clk_set_rate(sspa->sysclk, freq_out);
147*4882a593Smuzhiyun 		if (ret)
148*4882a593Smuzhiyun 			return ret;
149*4882a593Smuzhiyun 		break;
150*4882a593Smuzhiyun 	case MMP_SSPA_CLK:
151*4882a593Smuzhiyun 		ret = clk_set_rate(sspa->clk, freq_out);
152*4882a593Smuzhiyun 		if (ret)
153*4882a593Smuzhiyun 			return ret;
154*4882a593Smuzhiyun 		break;
155*4882a593Smuzhiyun 	default:
156*4882a593Smuzhiyun 		return -ENODEV;
157*4882a593Smuzhiyun 	}
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	return 0;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun /*
163*4882a593Smuzhiyun  * Set up the sspa dai format.
164*4882a593Smuzhiyun  */
mmp_sspa_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)165*4882a593Smuzhiyun static int mmp_sspa_set_dai_fmt(struct snd_soc_dai *cpu_dai,
166*4882a593Smuzhiyun 				 unsigned int fmt)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	/* reset port settings */
171*4882a593Smuzhiyun 	sspa->sp   = SSPA_SP_WEN | SSPA_SP_S_RST | SSPA_SP_FFLUSH;
172*4882a593Smuzhiyun 	sspa->ctrl = 0;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
175*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
176*4882a593Smuzhiyun 		sspa->sp |= SSPA_SP_MSL;
177*4882a593Smuzhiyun 		break;
178*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
179*4882a593Smuzhiyun 		break;
180*4882a593Smuzhiyun 	default:
181*4882a593Smuzhiyun 		return -EINVAL;
182*4882a593Smuzhiyun 	}
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
185*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_NB_NF:
186*4882a593Smuzhiyun 		sspa->sp |= SSPA_SP_FSP;
187*4882a593Smuzhiyun 		break;
188*4882a593Smuzhiyun 	default:
189*4882a593Smuzhiyun 		return -EINVAL;
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
193*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_I2S:
194*4882a593Smuzhiyun 		sspa->ctrl |= SSPA_CTL_XDATDLY(1);
195*4882a593Smuzhiyun 		break;
196*4882a593Smuzhiyun 	default:
197*4882a593Smuzhiyun 		return -EINVAL;
198*4882a593Smuzhiyun 	}
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/* Since we are configuring the timings for the format by hand
201*4882a593Smuzhiyun 	 * we have to defer some things until hw_params() where we
202*4882a593Smuzhiyun 	 * know parameters like the sample size.
203*4882a593Smuzhiyun 	 */
204*4882a593Smuzhiyun 	return 0;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun /*
208*4882a593Smuzhiyun  * Set the SSPA audio DMA parameters and sample size.
209*4882a593Smuzhiyun  * Can be called multiple times by oss emulation.
210*4882a593Smuzhiyun  */
mmp_sspa_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)211*4882a593Smuzhiyun static int mmp_sspa_hw_params(struct snd_pcm_substream *substream,
212*4882a593Smuzhiyun 			       struct snd_pcm_hw_params *params,
213*4882a593Smuzhiyun 			       struct snd_soc_dai *dai)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
216*4882a593Smuzhiyun 	struct device *dev = dai->component->dev;
217*4882a593Smuzhiyun 	u32 sspa_ctrl = sspa->ctrl;
218*4882a593Smuzhiyun 	int bits;
219*4882a593Smuzhiyun 	int bitval;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	switch (params_format(params)) {
222*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S8:
223*4882a593Smuzhiyun 		bits = 8;
224*4882a593Smuzhiyun 		bitval = SSPA_CTL_8_BITS;
225*4882a593Smuzhiyun 		break;
226*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S16_LE:
227*4882a593Smuzhiyun 		bits = 16;
228*4882a593Smuzhiyun 		bitval = SSPA_CTL_16_BITS;
229*4882a593Smuzhiyun 		break;
230*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S24_3LE:
231*4882a593Smuzhiyun 		bits = 24;
232*4882a593Smuzhiyun 		bitval = SSPA_CTL_24_BITS;
233*4882a593Smuzhiyun 		break;
234*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S32_LE:
235*4882a593Smuzhiyun 		bits = 32;
236*4882a593Smuzhiyun 		bitval = SSPA_CTL_32_BITS;
237*4882a593Smuzhiyun 		break;
238*4882a593Smuzhiyun 	default:
239*4882a593Smuzhiyun 		return -EINVAL;
240*4882a593Smuzhiyun 	}
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	if (dev->of_node || params_channels(params) == 2)
243*4882a593Smuzhiyun 		sspa_ctrl |= SSPA_CTL_XPH;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	sspa_ctrl &= ~SSPA_CTL_XWDLEN1_MASK;
246*4882a593Smuzhiyun 	sspa_ctrl |= SSPA_CTL_XWDLEN1(bitval);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	sspa_ctrl &= ~SSPA_CTL_XSSZ1_MASK;
249*4882a593Smuzhiyun 	sspa_ctrl |= SSPA_CTL_XSSZ1(bitval);
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	sspa_ctrl &= ~SSPA_CTL_XSSZ2_MASK;
252*4882a593Smuzhiyun 	sspa_ctrl |= SSPA_CTL_XSSZ2(bitval);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	sspa->sp &= ~SSPA_SP_FWID_MASK;
255*4882a593Smuzhiyun 	sspa->sp |= SSPA_SP_FWID(bits - 1);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	sspa->sp &= ~SSPA_TXSP_FPER_MASK;
258*4882a593Smuzhiyun 	sspa->sp |= SSPA_TXSP_FPER(bits * 2 - 1);
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	if (dev->of_node) {
261*4882a593Smuzhiyun 		clk_set_rate(sspa->clk, params_rate(params) *
262*4882a593Smuzhiyun 					params_channels(params) * bits);
263*4882a593Smuzhiyun 	}
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
266*4882a593Smuzhiyun 		__raw_writel(sspa_ctrl, sspa->tx_base + SSPA_CTL);
267*4882a593Smuzhiyun 		__raw_writel(0x1, sspa->tx_base + SSPA_FIFO_UL);
268*4882a593Smuzhiyun 	} else {
269*4882a593Smuzhiyun 		__raw_writel(sspa_ctrl, sspa->rx_base + SSPA_CTL);
270*4882a593Smuzhiyun 		__raw_writel(0x0, sspa->rx_base + SSPA_FIFO_UL);
271*4882a593Smuzhiyun 	}
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	return 0;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun 
mmp_sspa_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)276*4882a593Smuzhiyun static int mmp_sspa_trigger(struct snd_pcm_substream *substream, int cmd,
277*4882a593Smuzhiyun 			     struct snd_soc_dai *dai)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
280*4882a593Smuzhiyun 	int ret = 0;
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	switch (cmd) {
283*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_START:
284*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_RESUME:
285*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
286*4882a593Smuzhiyun 		/*
287*4882a593Smuzhiyun 		 * whatever playback or capture, must enable rx.
288*4882a593Smuzhiyun 		 * this is a hw issue, so need check if rx has been
289*4882a593Smuzhiyun 		 * enabled or not; if has been enabled by another
290*4882a593Smuzhiyun 		 * stream, do not enable again.
291*4882a593Smuzhiyun 		 */
292*4882a593Smuzhiyun 		if (!sspa->running_cnt)
293*4882a593Smuzhiyun 			mmp_sspa_rx_enable(sspa);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
296*4882a593Smuzhiyun 			mmp_sspa_tx_enable(sspa);
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 		sspa->running_cnt++;
299*4882a593Smuzhiyun 		break;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_STOP:
302*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_SUSPEND:
303*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
304*4882a593Smuzhiyun 		sspa->running_cnt--;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
307*4882a593Smuzhiyun 			mmp_sspa_tx_disable(sspa);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 		/* have no capture stream, disable rx port */
310*4882a593Smuzhiyun 		if (!sspa->running_cnt)
311*4882a593Smuzhiyun 			mmp_sspa_rx_disable(sspa);
312*4882a593Smuzhiyun 		break;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	default:
315*4882a593Smuzhiyun 		ret = -EINVAL;
316*4882a593Smuzhiyun 	}
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	return ret;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun 
mmp_sspa_probe(struct snd_soc_dai * dai)321*4882a593Smuzhiyun static int mmp_sspa_probe(struct snd_soc_dai *dai)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun 	struct sspa_priv *sspa = dev_get_drvdata(dai->dev);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	snd_soc_dai_init_dma_data(dai,
326*4882a593Smuzhiyun 				&sspa->playback_dma_data,
327*4882a593Smuzhiyun 				&sspa->capture_dma_data);
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	snd_soc_dai_set_drvdata(dai, sspa);
330*4882a593Smuzhiyun 	return 0;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun #define MMP_SSPA_RATES SNDRV_PCM_RATE_8000_192000
334*4882a593Smuzhiyun #define MMP_SSPA_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
335*4882a593Smuzhiyun 		SNDRV_PCM_FMTBIT_S16_LE | \
336*4882a593Smuzhiyun 		SNDRV_PCM_FMTBIT_S24_3LE | \
337*4882a593Smuzhiyun 		SNDRV_PCM_FMTBIT_S32_LE)
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun static const struct snd_soc_dai_ops mmp_sspa_dai_ops = {
340*4882a593Smuzhiyun 	.startup	= mmp_sspa_startup,
341*4882a593Smuzhiyun 	.shutdown	= mmp_sspa_shutdown,
342*4882a593Smuzhiyun 	.trigger	= mmp_sspa_trigger,
343*4882a593Smuzhiyun 	.hw_params	= mmp_sspa_hw_params,
344*4882a593Smuzhiyun 	.set_sysclk	= mmp_sspa_set_dai_sysclk,
345*4882a593Smuzhiyun 	.set_pll	= mmp_sspa_set_dai_pll,
346*4882a593Smuzhiyun 	.set_fmt	= mmp_sspa_set_dai_fmt,
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun static struct snd_soc_dai_driver mmp_sspa_dai = {
350*4882a593Smuzhiyun 	.probe = mmp_sspa_probe,
351*4882a593Smuzhiyun 	.playback = {
352*4882a593Smuzhiyun 		.channels_min = 1,
353*4882a593Smuzhiyun 		.channels_max = 128,
354*4882a593Smuzhiyun 		.rates = MMP_SSPA_RATES,
355*4882a593Smuzhiyun 		.formats = MMP_SSPA_FORMATS,
356*4882a593Smuzhiyun 	},
357*4882a593Smuzhiyun 	.capture = {
358*4882a593Smuzhiyun 		.channels_min = 1,
359*4882a593Smuzhiyun 		.channels_max = 2,
360*4882a593Smuzhiyun 		.rates = MMP_SSPA_RATES,
361*4882a593Smuzhiyun 		.formats = MMP_SSPA_FORMATS,
362*4882a593Smuzhiyun 	},
363*4882a593Smuzhiyun 	.ops = &mmp_sspa_dai_ops,
364*4882a593Smuzhiyun };
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun #define MMP_PCM_INFO (SNDRV_PCM_INFO_MMAP |	\
367*4882a593Smuzhiyun 		SNDRV_PCM_INFO_MMAP_VALID |	\
368*4882a593Smuzhiyun 		SNDRV_PCM_INFO_INTERLEAVED |	\
369*4882a593Smuzhiyun 		SNDRV_PCM_INFO_PAUSE |		\
370*4882a593Smuzhiyun 		SNDRV_PCM_INFO_RESUME |		\
371*4882a593Smuzhiyun 		SNDRV_PCM_INFO_NO_PERIOD_WAKEUP)
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun static const struct snd_pcm_hardware mmp_pcm_hardware[] = {
374*4882a593Smuzhiyun 	{
375*4882a593Smuzhiyun 		.info			= MMP_PCM_INFO,
376*4882a593Smuzhiyun 		.period_bytes_min	= 1024,
377*4882a593Smuzhiyun 		.period_bytes_max	= 2048,
378*4882a593Smuzhiyun 		.periods_min		= 2,
379*4882a593Smuzhiyun 		.periods_max		= 32,
380*4882a593Smuzhiyun 		.buffer_bytes_max	= 4096,
381*4882a593Smuzhiyun 		.fifo_size		= 32,
382*4882a593Smuzhiyun 	},
383*4882a593Smuzhiyun 	{
384*4882a593Smuzhiyun 		.info			= MMP_PCM_INFO,
385*4882a593Smuzhiyun 		.period_bytes_min	= 1024,
386*4882a593Smuzhiyun 		.period_bytes_max	= 2048,
387*4882a593Smuzhiyun 		.periods_min		= 2,
388*4882a593Smuzhiyun 		.periods_max		= 32,
389*4882a593Smuzhiyun 		.buffer_bytes_max	= 4096,
390*4882a593Smuzhiyun 		.fifo_size		= 32,
391*4882a593Smuzhiyun 	},
392*4882a593Smuzhiyun };
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun static const struct snd_dmaengine_pcm_config mmp_pcm_config = {
395*4882a593Smuzhiyun 	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
396*4882a593Smuzhiyun 	.pcm_hardware = mmp_pcm_hardware,
397*4882a593Smuzhiyun 	.prealloc_buffer_size = 4096,
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun 
mmp_pcm_mmap(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct vm_area_struct * vma)400*4882a593Smuzhiyun static int mmp_pcm_mmap(struct snd_soc_component *component,
401*4882a593Smuzhiyun 			struct snd_pcm_substream *substream,
402*4882a593Smuzhiyun 			struct vm_area_struct *vma)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun 	vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;
405*4882a593Smuzhiyun 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
406*4882a593Smuzhiyun 	return remap_pfn_range(vma, vma->vm_start,
407*4882a593Smuzhiyun 		substream->dma_buffer.addr >> PAGE_SHIFT,
408*4882a593Smuzhiyun 		vma->vm_end - vma->vm_start, vma->vm_page_prot);
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun 
mmp_sspa_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)411*4882a593Smuzhiyun static int mmp_sspa_open(struct snd_soc_component *component,
412*4882a593Smuzhiyun 			 struct snd_pcm_substream *substream)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun 	struct sspa_priv *sspa = snd_soc_component_get_drvdata(component);
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	pm_runtime_get_sync(component->dev);
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 	/* we can only change the settings if the port is not in use */
419*4882a593Smuzhiyun 	if ((__raw_readl(sspa->tx_base + SSPA_SP) & SSPA_SP_S_EN) ||
420*4882a593Smuzhiyun 	    (__raw_readl(sspa->rx_base + SSPA_SP) & SSPA_SP_S_EN)) {
421*4882a593Smuzhiyun 		dev_err(component->dev,
422*4882a593Smuzhiyun 			"can't change hardware dai format: stream is in use\n");
423*4882a593Smuzhiyun 		return -EBUSY;
424*4882a593Smuzhiyun 	}
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
427*4882a593Smuzhiyun 	__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	sspa->sp &= ~(SSPA_SP_S_RST | SSPA_SP_FFLUSH);
430*4882a593Smuzhiyun 	__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
431*4882a593Smuzhiyun 	__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	/*
434*4882a593Smuzhiyun 	 * FIXME: hw issue, for the tx serial port,
435*4882a593Smuzhiyun 	 * can not config the master/slave mode;
436*4882a593Smuzhiyun 	 * so must clean this bit.
437*4882a593Smuzhiyun 	 * The master/slave mode has been set in the
438*4882a593Smuzhiyun 	 * rx port.
439*4882a593Smuzhiyun 	 */
440*4882a593Smuzhiyun 	__raw_writel(sspa->sp & ~SSPA_SP_MSL, sspa->tx_base + SSPA_SP);
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	__raw_writel(sspa->ctrl, sspa->tx_base + SSPA_CTL);
443*4882a593Smuzhiyun 	__raw_writel(sspa->ctrl, sspa->rx_base + SSPA_CTL);
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	return 0;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun 
mmp_sspa_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)448*4882a593Smuzhiyun static int mmp_sspa_close(struct snd_soc_component *component,
449*4882a593Smuzhiyun 			  struct snd_pcm_substream *substream)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun 	pm_runtime_put_sync(component->dev);
452*4882a593Smuzhiyun 	return 0;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun static const struct snd_soc_component_driver mmp_sspa_component = {
456*4882a593Smuzhiyun 	.name		= "mmp-sspa",
457*4882a593Smuzhiyun 	.mmap		= mmp_pcm_mmap,
458*4882a593Smuzhiyun 	.open		= mmp_sspa_open,
459*4882a593Smuzhiyun 	.close		= mmp_sspa_close,
460*4882a593Smuzhiyun };
461*4882a593Smuzhiyun 
asoc_mmp_sspa_probe(struct platform_device * pdev)462*4882a593Smuzhiyun static int asoc_mmp_sspa_probe(struct platform_device *pdev)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun 	struct sspa_priv *sspa;
465*4882a593Smuzhiyun 	int ret;
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	sspa = devm_kzalloc(&pdev->dev,
468*4882a593Smuzhiyun 				sizeof(struct sspa_priv), GFP_KERNEL);
469*4882a593Smuzhiyun 	if (!sspa)
470*4882a593Smuzhiyun 		return -ENOMEM;
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	if (pdev->dev.of_node) {
473*4882a593Smuzhiyun 		sspa->rx_base = devm_platform_ioremap_resource(pdev, 0);
474*4882a593Smuzhiyun 		if (IS_ERR(sspa->rx_base))
475*4882a593Smuzhiyun 			return PTR_ERR(sspa->rx_base);
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 		sspa->tx_base = devm_platform_ioremap_resource(pdev, 1);
478*4882a593Smuzhiyun 		if (IS_ERR(sspa->tx_base))
479*4882a593Smuzhiyun 			return PTR_ERR(sspa->tx_base);
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 		sspa->clk = devm_clk_get(&pdev->dev, "bitclk");
482*4882a593Smuzhiyun 		if (IS_ERR(sspa->clk))
483*4882a593Smuzhiyun 			return PTR_ERR(sspa->clk);
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 		sspa->audio_clk = devm_clk_get(&pdev->dev, "audio");
486*4882a593Smuzhiyun 		if (IS_ERR(sspa->audio_clk))
487*4882a593Smuzhiyun 			return PTR_ERR(sspa->audio_clk);
488*4882a593Smuzhiyun 	} else {
489*4882a593Smuzhiyun 		struct resource *res;
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 		res = platform_get_resource(pdev, IORESOURCE_IO, 0);
492*4882a593Smuzhiyun 		if (res == NULL)
493*4882a593Smuzhiyun 			return -ENODEV;
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 		sspa->rx_base = devm_ioremap(&pdev->dev, res->start, 0x30);
496*4882a593Smuzhiyun 		if (!sspa->rx_base)
497*4882a593Smuzhiyun 			return -ENOMEM;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 		sspa->tx_base = devm_ioremap(&pdev->dev,
500*4882a593Smuzhiyun 					     res->start + 0x80, 0x30);
501*4882a593Smuzhiyun 		if (!sspa->tx_base)
502*4882a593Smuzhiyun 			return -ENOMEM;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 		sspa->clk = devm_clk_get(&pdev->dev, NULL);
505*4882a593Smuzhiyun 		if (IS_ERR(sspa->clk))
506*4882a593Smuzhiyun 			return PTR_ERR(sspa->clk);
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 		sspa->audio_clk = clk_get(NULL, "mmp-audio");
509*4882a593Smuzhiyun 		if (IS_ERR(sspa->audio_clk))
510*4882a593Smuzhiyun 			return PTR_ERR(sspa->audio_clk);
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 		sspa->sysclk = clk_get(NULL, "mmp-sysclk");
513*4882a593Smuzhiyun 		if (IS_ERR(sspa->sysclk)) {
514*4882a593Smuzhiyun 			clk_put(sspa->audio_clk);
515*4882a593Smuzhiyun 			return PTR_ERR(sspa->sysclk);
516*4882a593Smuzhiyun 		}
517*4882a593Smuzhiyun 	}
518*4882a593Smuzhiyun 	platform_set_drvdata(pdev, sspa);
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	sspa->playback_dma_data.maxburst = 4;
521*4882a593Smuzhiyun 	sspa->capture_dma_data.maxburst = 4;
522*4882a593Smuzhiyun 	/* You know, these addresses are actually ignored. */
523*4882a593Smuzhiyun 	sspa->capture_dma_data.addr = SSPA_D;
524*4882a593Smuzhiyun 	sspa->playback_dma_data.addr = 0x80 + SSPA_D;
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 	if (pdev->dev.of_node) {
527*4882a593Smuzhiyun 		ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
528*4882a593Smuzhiyun 						      &mmp_pcm_config, 0);
529*4882a593Smuzhiyun 		if (ret)
530*4882a593Smuzhiyun 			return ret;
531*4882a593Smuzhiyun 	}
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(&pdev->dev, &mmp_sspa_component,
534*4882a593Smuzhiyun 					      &mmp_sspa_dai, 1);
535*4882a593Smuzhiyun 	if (ret)
536*4882a593Smuzhiyun 		return ret;
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	pm_runtime_enable(&pdev->dev);
539*4882a593Smuzhiyun 	clk_prepare_enable(sspa->audio_clk);
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	return 0;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun 
asoc_mmp_sspa_remove(struct platform_device * pdev)544*4882a593Smuzhiyun static int asoc_mmp_sspa_remove(struct platform_device *pdev)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun 	struct sspa_priv *sspa = platform_get_drvdata(pdev);
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	clk_disable_unprepare(sspa->audio_clk);
549*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	if (pdev->dev.of_node)
552*4882a593Smuzhiyun 		return 0;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	clk_put(sspa->audio_clk);
555*4882a593Smuzhiyun 	clk_put(sspa->sysclk);
556*4882a593Smuzhiyun 	return 0;
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun #ifdef CONFIG_OF
560*4882a593Smuzhiyun static const struct of_device_id mmp_sspa_of_match[] = {
561*4882a593Smuzhiyun 	{ .compatible = "marvell,mmp-sspa" },
562*4882a593Smuzhiyun 	{},
563*4882a593Smuzhiyun };
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mmp_sspa_of_match);
566*4882a593Smuzhiyun #endif
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun static struct platform_driver asoc_mmp_sspa_driver = {
569*4882a593Smuzhiyun 	.driver = {
570*4882a593Smuzhiyun 		.name = "mmp-sspa-dai",
571*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(mmp_sspa_of_match),
572*4882a593Smuzhiyun 	},
573*4882a593Smuzhiyun 	.probe = asoc_mmp_sspa_probe,
574*4882a593Smuzhiyun 	.remove = asoc_mmp_sspa_remove,
575*4882a593Smuzhiyun };
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun module_platform_driver(asoc_mmp_sspa_driver);
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
580*4882a593Smuzhiyun MODULE_DESCRIPTION("MMP SSPA SoC Interface");
581*4882a593Smuzhiyun MODULE_LICENSE("GPL");
582*4882a593Smuzhiyun MODULE_ALIAS("platform:mmp-sspa-dai");
583