1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2020 BayLibre, SAS.
4*4882a593Smuzhiyun // Author: Jerome Brunet <jbrunet@baylibre.com>
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
11*4882a593Smuzhiyun #include <linux/reset.h>
12*4882a593Smuzhiyun #include <sound/soc.h>
13*4882a593Smuzhiyun #include <sound/tlv.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define BLOCK_EN 0x00
16*4882a593Smuzhiyun #define LORN_EN 0
17*4882a593Smuzhiyun #define LORP_EN 1
18*4882a593Smuzhiyun #define LOLN_EN 2
19*4882a593Smuzhiyun #define LOLP_EN 3
20*4882a593Smuzhiyun #define DACR_EN 4
21*4882a593Smuzhiyun #define DACL_EN 5
22*4882a593Smuzhiyun #define DACR_INV 20
23*4882a593Smuzhiyun #define DACL_INV 21
24*4882a593Smuzhiyun #define DACR_SRC 22
25*4882a593Smuzhiyun #define DACL_SRC 23
26*4882a593Smuzhiyun #define REFP_BUF_EN BIT(12)
27*4882a593Smuzhiyun #define BIAS_CURRENT_EN BIT(13)
28*4882a593Smuzhiyun #define VMID_GEN_FAST BIT(14)
29*4882a593Smuzhiyun #define VMID_GEN_EN BIT(15)
30*4882a593Smuzhiyun #define I2S_MODE BIT(30)
31*4882a593Smuzhiyun #define VOL_CTRL0 0x04
32*4882a593Smuzhiyun #define GAIN_H 31
33*4882a593Smuzhiyun #define GAIN_L 23
34*4882a593Smuzhiyun #define VOL_CTRL1 0x08
35*4882a593Smuzhiyun #define DAC_MONO 8
36*4882a593Smuzhiyun #define RAMP_RATE 10
37*4882a593Smuzhiyun #define VC_RAMP_MODE 12
38*4882a593Smuzhiyun #define MUTE_MODE 13
39*4882a593Smuzhiyun #define UNMUTE_MODE 14
40*4882a593Smuzhiyun #define DAC_SOFT_MUTE 15
41*4882a593Smuzhiyun #define DACR_VC 16
42*4882a593Smuzhiyun #define DACL_VC 24
43*4882a593Smuzhiyun #define LINEOUT_CFG 0x0c
44*4882a593Smuzhiyun #define LORN_POL 0
45*4882a593Smuzhiyun #define LORP_POL 4
46*4882a593Smuzhiyun #define LOLN_POL 8
47*4882a593Smuzhiyun #define LOLP_POL 12
48*4882a593Smuzhiyun #define POWER_CFG 0x10
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun struct t9015 {
51*4882a593Smuzhiyun struct clk *pclk;
52*4882a593Smuzhiyun struct regulator *avdd;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
t9015_dai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)55*4882a593Smuzhiyun static int t9015_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
58*4882a593Smuzhiyun unsigned int val;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
61*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
62*4882a593Smuzhiyun val = I2S_MODE;
63*4882a593Smuzhiyun break;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
66*4882a593Smuzhiyun val = 0;
67*4882a593Smuzhiyun break;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun default:
70*4882a593Smuzhiyun return -EINVAL;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun snd_soc_component_update_bits(component, BLOCK_EN, I2S_MODE, val);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S) &&
76*4882a593Smuzhiyun ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_LEFT_J))
77*4882a593Smuzhiyun return -EINVAL;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const struct snd_soc_dai_ops t9015_dai_ops = {
83*4882a593Smuzhiyun .set_fmt = t9015_dai_set_fmt,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static struct snd_soc_dai_driver t9015_dai = {
87*4882a593Smuzhiyun .name = "t9015-hifi",
88*4882a593Smuzhiyun .playback = {
89*4882a593Smuzhiyun .stream_name = "Playback",
90*4882a593Smuzhiyun .channels_min = 1,
91*4882a593Smuzhiyun .channels_max = 2,
92*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_96000,
93*4882a593Smuzhiyun .formats = (SNDRV_PCM_FMTBIT_S8 |
94*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S16_LE |
95*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S20_LE |
96*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE),
97*4882a593Smuzhiyun },
98*4882a593Smuzhiyun .ops = &t9015_dai_ops,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const DECLARE_TLV_DB_MINMAX_MUTE(dac_vol_tlv, -9525, 0);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const char * const ramp_rate_txt[] = { "Fast", "Slow" };
104*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(ramp_rate_enum, VOL_CTRL1, RAMP_RATE,
105*4882a593Smuzhiyun ramp_rate_txt);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static const char * const dacr_in_txt[] = { "Right", "Left" };
108*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(dacr_in_enum, BLOCK_EN, DACR_SRC, dacr_in_txt);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static const char * const dacl_in_txt[] = { "Left", "Right" };
111*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(dacl_in_enum, BLOCK_EN, DACL_SRC, dacl_in_txt);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun static const char * const mono_txt[] = { "Stereo", "Mono"};
114*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(mono_enum, VOL_CTRL1, DAC_MONO, mono_txt);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static const struct snd_kcontrol_new t9015_snd_controls[] = {
117*4882a593Smuzhiyun /* Volume Controls */
118*4882a593Smuzhiyun SOC_ENUM("Playback Channel Mode", mono_enum),
119*4882a593Smuzhiyun SOC_SINGLE("Playback Switch", VOL_CTRL1, DAC_SOFT_MUTE, 1, 1),
120*4882a593Smuzhiyun SOC_DOUBLE_TLV("Playback Volume", VOL_CTRL1, DACL_VC, DACR_VC,
121*4882a593Smuzhiyun 0xff, 0, dac_vol_tlv),
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* Ramp Controls */
124*4882a593Smuzhiyun SOC_ENUM("Ramp Rate", ramp_rate_enum),
125*4882a593Smuzhiyun SOC_SINGLE("Volume Ramp Switch", VOL_CTRL1, VC_RAMP_MODE, 1, 0),
126*4882a593Smuzhiyun SOC_SINGLE("Mute Ramp Switch", VOL_CTRL1, MUTE_MODE, 1, 0),
127*4882a593Smuzhiyun SOC_SINGLE("Unmute Ramp Switch", VOL_CTRL1, UNMUTE_MODE, 1, 0),
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun static const struct snd_kcontrol_new t9015_right_dac_mux =
131*4882a593Smuzhiyun SOC_DAPM_ENUM("Right DAC Source", dacr_in_enum);
132*4882a593Smuzhiyun static const struct snd_kcontrol_new t9015_left_dac_mux =
133*4882a593Smuzhiyun SOC_DAPM_ENUM("Left DAC Source", dacl_in_enum);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun static const struct snd_soc_dapm_widget t9015_dapm_widgets[] = {
136*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("Right IN", NULL, 0, SND_SOC_NOPM, 0, 0),
137*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("Left IN", NULL, 0, SND_SOC_NOPM, 0, 0),
138*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Right DAC Sel", SND_SOC_NOPM, 0, 0,
139*4882a593Smuzhiyun &t9015_right_dac_mux),
140*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Left DAC Sel", SND_SOC_NOPM, 0, 0,
141*4882a593Smuzhiyun &t9015_left_dac_mux),
142*4882a593Smuzhiyun SND_SOC_DAPM_DAC("Right DAC", NULL, BLOCK_EN, DACR_EN, 0),
143*4882a593Smuzhiyun SND_SOC_DAPM_DAC("Left DAC", NULL, BLOCK_EN, DACL_EN, 0),
144*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("Right- Driver", BLOCK_EN, LORN_EN, 0,
145*4882a593Smuzhiyun NULL, 0),
146*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("Right+ Driver", BLOCK_EN, LORP_EN, 0,
147*4882a593Smuzhiyun NULL, 0),
148*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("Left- Driver", BLOCK_EN, LOLN_EN, 0,
149*4882a593Smuzhiyun NULL, 0),
150*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("Left+ Driver", BLOCK_EN, LOLP_EN, 0,
151*4882a593Smuzhiyun NULL, 0),
152*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LORN"),
153*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LORP"),
154*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LOLN"),
155*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LOLP"),
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun static const struct snd_soc_dapm_route t9015_dapm_routes[] = {
159*4882a593Smuzhiyun { "Right IN", NULL, "Playback" },
160*4882a593Smuzhiyun { "Left IN", NULL, "Playback" },
161*4882a593Smuzhiyun { "Right DAC Sel", "Right", "Right IN" },
162*4882a593Smuzhiyun { "Right DAC Sel", "Left", "Left IN" },
163*4882a593Smuzhiyun { "Left DAC Sel", "Right", "Right IN" },
164*4882a593Smuzhiyun { "Left DAC Sel", "Left", "Left IN" },
165*4882a593Smuzhiyun { "Right DAC", NULL, "Right DAC Sel" },
166*4882a593Smuzhiyun { "Left DAC", NULL, "Left DAC Sel" },
167*4882a593Smuzhiyun { "Right- Driver", NULL, "Right DAC" },
168*4882a593Smuzhiyun { "Right+ Driver", NULL, "Right DAC" },
169*4882a593Smuzhiyun { "Left- Driver", NULL, "Left DAC" },
170*4882a593Smuzhiyun { "Left+ Driver", NULL, "Left DAC" },
171*4882a593Smuzhiyun { "LORN", NULL, "Right- Driver", },
172*4882a593Smuzhiyun { "LORP", NULL, "Right+ Driver", },
173*4882a593Smuzhiyun { "LOLN", NULL, "Left- Driver", },
174*4882a593Smuzhiyun { "LOLP", NULL, "Left+ Driver", },
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun
t9015_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)177*4882a593Smuzhiyun static int t9015_set_bias_level(struct snd_soc_component *component,
178*4882a593Smuzhiyun enum snd_soc_bias_level level)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun struct t9015 *priv = snd_soc_component_get_drvdata(component);
181*4882a593Smuzhiyun enum snd_soc_bias_level now =
182*4882a593Smuzhiyun snd_soc_component_get_bias_level(component);
183*4882a593Smuzhiyun int ret;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun switch (level) {
186*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
187*4882a593Smuzhiyun snd_soc_component_update_bits(component, BLOCK_EN,
188*4882a593Smuzhiyun BIAS_CURRENT_EN,
189*4882a593Smuzhiyun BIAS_CURRENT_EN);
190*4882a593Smuzhiyun break;
191*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
192*4882a593Smuzhiyun snd_soc_component_update_bits(component, BLOCK_EN,
193*4882a593Smuzhiyun BIAS_CURRENT_EN,
194*4882a593Smuzhiyun 0);
195*4882a593Smuzhiyun break;
196*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
197*4882a593Smuzhiyun ret = regulator_enable(priv->avdd);
198*4882a593Smuzhiyun if (ret) {
199*4882a593Smuzhiyun dev_err(component->dev, "AVDD enable failed\n");
200*4882a593Smuzhiyun return ret;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun if (now == SND_SOC_BIAS_OFF) {
204*4882a593Smuzhiyun snd_soc_component_update_bits(component, BLOCK_EN,
205*4882a593Smuzhiyun VMID_GEN_EN | VMID_GEN_FAST | REFP_BUF_EN,
206*4882a593Smuzhiyun VMID_GEN_EN | VMID_GEN_FAST | REFP_BUF_EN);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun mdelay(200);
209*4882a593Smuzhiyun snd_soc_component_update_bits(component, BLOCK_EN,
210*4882a593Smuzhiyun VMID_GEN_FAST,
211*4882a593Smuzhiyun 0);
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun break;
215*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
216*4882a593Smuzhiyun snd_soc_component_update_bits(component, BLOCK_EN,
217*4882a593Smuzhiyun VMID_GEN_EN | VMID_GEN_FAST | REFP_BUF_EN,
218*4882a593Smuzhiyun 0);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun regulator_disable(priv->avdd);
221*4882a593Smuzhiyun break;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun return 0;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun static const struct snd_soc_component_driver t9015_codec_driver = {
228*4882a593Smuzhiyun .set_bias_level = t9015_set_bias_level,
229*4882a593Smuzhiyun .controls = t9015_snd_controls,
230*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(t9015_snd_controls),
231*4882a593Smuzhiyun .dapm_widgets = t9015_dapm_widgets,
232*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(t9015_dapm_widgets),
233*4882a593Smuzhiyun .dapm_routes = t9015_dapm_routes,
234*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(t9015_dapm_routes),
235*4882a593Smuzhiyun .suspend_bias_off = 1,
236*4882a593Smuzhiyun .endianness = 1,
237*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun static const struct regmap_config t9015_regmap_config = {
241*4882a593Smuzhiyun .reg_bits = 32,
242*4882a593Smuzhiyun .reg_stride = 4,
243*4882a593Smuzhiyun .val_bits = 32,
244*4882a593Smuzhiyun .max_register = POWER_CFG,
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
t9015_probe(struct platform_device * pdev)247*4882a593Smuzhiyun static int t9015_probe(struct platform_device *pdev)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun struct device *dev = &pdev->dev;
250*4882a593Smuzhiyun struct t9015 *priv;
251*4882a593Smuzhiyun void __iomem *regs;
252*4882a593Smuzhiyun struct regmap *regmap;
253*4882a593Smuzhiyun int ret;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
256*4882a593Smuzhiyun if (!priv)
257*4882a593Smuzhiyun return -ENOMEM;
258*4882a593Smuzhiyun platform_set_drvdata(pdev, priv);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun priv->pclk = devm_clk_get(dev, "pclk");
261*4882a593Smuzhiyun if (IS_ERR(priv->pclk)) {
262*4882a593Smuzhiyun if (PTR_ERR(priv->pclk) != -EPROBE_DEFER)
263*4882a593Smuzhiyun dev_err(dev, "failed to get core clock\n");
264*4882a593Smuzhiyun return PTR_ERR(priv->pclk);
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun priv->avdd = devm_regulator_get(dev, "AVDD");
268*4882a593Smuzhiyun if (IS_ERR(priv->avdd)) {
269*4882a593Smuzhiyun if (PTR_ERR(priv->avdd) != -EPROBE_DEFER)
270*4882a593Smuzhiyun dev_err(dev, "failed to AVDD\n");
271*4882a593Smuzhiyun return PTR_ERR(priv->avdd);
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun ret = clk_prepare_enable(priv->pclk);
275*4882a593Smuzhiyun if (ret) {
276*4882a593Smuzhiyun dev_err(dev, "core clock enable failed\n");
277*4882a593Smuzhiyun return ret;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun ret = devm_add_action_or_reset(dev,
281*4882a593Smuzhiyun (void(*)(void *))clk_disable_unprepare,
282*4882a593Smuzhiyun priv->pclk);
283*4882a593Smuzhiyun if (ret)
284*4882a593Smuzhiyun return ret;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun ret = device_reset(dev);
287*4882a593Smuzhiyun if (ret) {
288*4882a593Smuzhiyun dev_err(dev, "reset failed\n");
289*4882a593Smuzhiyun return ret;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun regs = devm_platform_ioremap_resource(pdev, 0);
293*4882a593Smuzhiyun if (IS_ERR(regs)) {
294*4882a593Smuzhiyun dev_err(dev, "register map failed\n");
295*4882a593Smuzhiyun return PTR_ERR(regs);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun regmap = devm_regmap_init_mmio(dev, regs, &t9015_regmap_config);
299*4882a593Smuzhiyun if (IS_ERR(regmap)) {
300*4882a593Smuzhiyun dev_err(dev, "regmap init failed\n");
301*4882a593Smuzhiyun return PTR_ERR(regmap);
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /*
305*4882a593Smuzhiyun * Initialize output polarity:
306*4882a593Smuzhiyun * ATM the output polarity is fixed but in the future it might useful
307*4882a593Smuzhiyun * to add DT property to set this depending on the platform needs
308*4882a593Smuzhiyun */
309*4882a593Smuzhiyun regmap_write(regmap, LINEOUT_CFG, 0x1111);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun return devm_snd_soc_register_component(dev, &t9015_codec_driver,
312*4882a593Smuzhiyun &t9015_dai, 1);
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun static const struct of_device_id t9015_ids[] = {
316*4882a593Smuzhiyun { .compatible = "amlogic,t9015", },
317*4882a593Smuzhiyun { }
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, t9015_ids);
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun static struct platform_driver t9015_driver = {
322*4882a593Smuzhiyun .driver = {
323*4882a593Smuzhiyun .name = "t9015-codec",
324*4882a593Smuzhiyun .of_match_table = of_match_ptr(t9015_ids),
325*4882a593Smuzhiyun },
326*4882a593Smuzhiyun .probe = t9015_probe,
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun module_platform_driver(t9015_driver);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC Amlogic T9015 codec driver");
332*4882a593Smuzhiyun MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
333*4882a593Smuzhiyun MODULE_LICENSE("GPL");
334