1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2019 BayLibre, SAS.
4*4882a593Smuzhiyun // Author: Jerome Brunet <jbrunet@baylibre.com>
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/bitfield.h>
7*4882a593Smuzhiyun #include <linux/clk.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <sound/pcm_params.h>
10*4882a593Smuzhiyun #include <linux/regmap.h>
11*4882a593Smuzhiyun #include <linux/reset.h>
12*4882a593Smuzhiyun #include <sound/soc.h>
13*4882a593Smuzhiyun #include <sound/soc-dai.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
16*4882a593Smuzhiyun #include "meson-codec-glue.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define G12A_TOHDMITX_DRV_NAME "g12a-tohdmitx"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define TOHDMITX_CTRL0 0x0
21*4882a593Smuzhiyun #define CTRL0_ENABLE_SHIFT 31
22*4882a593Smuzhiyun #define CTRL0_I2S_DAT_SEL_SHIFT 12
23*4882a593Smuzhiyun #define CTRL0_I2S_DAT_SEL (0x3 << CTRL0_I2S_DAT_SEL_SHIFT)
24*4882a593Smuzhiyun #define CTRL0_I2S_LRCLK_SEL GENMASK(9, 8)
25*4882a593Smuzhiyun #define CTRL0_I2S_BLK_CAP_INV BIT(7)
26*4882a593Smuzhiyun #define CTRL0_I2S_BCLK_O_INV BIT(6)
27*4882a593Smuzhiyun #define CTRL0_I2S_BCLK_SEL GENMASK(5, 4)
28*4882a593Smuzhiyun #define CTRL0_SPDIF_CLK_CAP_INV BIT(3)
29*4882a593Smuzhiyun #define CTRL0_SPDIF_CLK_O_INV BIT(2)
30*4882a593Smuzhiyun #define CTRL0_SPDIF_SEL_SHIFT 1
31*4882a593Smuzhiyun #define CTRL0_SPDIF_SEL (0x1 << CTRL0_SPDIF_SEL_SHIFT)
32*4882a593Smuzhiyun #define CTRL0_SPDIF_CLK_SEL BIT(0)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static const char * const g12a_tohdmitx_i2s_mux_texts[] = {
35*4882a593Smuzhiyun "I2S A", "I2S B", "I2S C",
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
g12a_tohdmitx_i2s_mux_put_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)38*4882a593Smuzhiyun static int g12a_tohdmitx_i2s_mux_put_enum(struct snd_kcontrol *kcontrol,
39*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct snd_soc_component *component =
42*4882a593Smuzhiyun snd_soc_dapm_kcontrol_component(kcontrol);
43*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm =
44*4882a593Smuzhiyun snd_soc_dapm_kcontrol_dapm(kcontrol);
45*4882a593Smuzhiyun struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
46*4882a593Smuzhiyun unsigned int mux, changed;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
49*4882a593Smuzhiyun changed = snd_soc_component_test_bits(component, e->reg,
50*4882a593Smuzhiyun CTRL0_I2S_DAT_SEL,
51*4882a593Smuzhiyun FIELD_PREP(CTRL0_I2S_DAT_SEL,
52*4882a593Smuzhiyun mux));
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun if (!changed)
55*4882a593Smuzhiyun return 0;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* Force disconnect of the mux while updating */
58*4882a593Smuzhiyun snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun snd_soc_component_update_bits(component, e->reg,
61*4882a593Smuzhiyun CTRL0_I2S_DAT_SEL |
62*4882a593Smuzhiyun CTRL0_I2S_LRCLK_SEL |
63*4882a593Smuzhiyun CTRL0_I2S_BCLK_SEL,
64*4882a593Smuzhiyun FIELD_PREP(CTRL0_I2S_DAT_SEL, mux) |
65*4882a593Smuzhiyun FIELD_PREP(CTRL0_I2S_LRCLK_SEL, mux) |
66*4882a593Smuzhiyun FIELD_PREP(CTRL0_I2S_BCLK_SEL, mux));
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return 1;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(g12a_tohdmitx_i2s_mux_enum, TOHDMITX_CTRL0,
74*4882a593Smuzhiyun CTRL0_I2S_DAT_SEL_SHIFT,
75*4882a593Smuzhiyun g12a_tohdmitx_i2s_mux_texts);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static const struct snd_kcontrol_new g12a_tohdmitx_i2s_mux =
78*4882a593Smuzhiyun SOC_DAPM_ENUM_EXT("I2S Source", g12a_tohdmitx_i2s_mux_enum,
79*4882a593Smuzhiyun snd_soc_dapm_get_enum_double,
80*4882a593Smuzhiyun g12a_tohdmitx_i2s_mux_put_enum);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const char * const g12a_tohdmitx_spdif_mux_texts[] = {
83*4882a593Smuzhiyun "SPDIF A", "SPDIF B",
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
g12a_tohdmitx_spdif_mux_put_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)86*4882a593Smuzhiyun static int g12a_tohdmitx_spdif_mux_put_enum(struct snd_kcontrol *kcontrol,
87*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct snd_soc_component *component =
90*4882a593Smuzhiyun snd_soc_dapm_kcontrol_component(kcontrol);
91*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm =
92*4882a593Smuzhiyun snd_soc_dapm_kcontrol_dapm(kcontrol);
93*4882a593Smuzhiyun struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
94*4882a593Smuzhiyun unsigned int mux, changed;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
97*4882a593Smuzhiyun changed = snd_soc_component_test_bits(component, TOHDMITX_CTRL0,
98*4882a593Smuzhiyun CTRL0_SPDIF_SEL,
99*4882a593Smuzhiyun FIELD_PREP(CTRL0_SPDIF_SEL, mux));
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if (!changed)
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* Force disconnect of the mux while updating */
105*4882a593Smuzhiyun snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun snd_soc_component_update_bits(component, TOHDMITX_CTRL0,
108*4882a593Smuzhiyun CTRL0_SPDIF_SEL |
109*4882a593Smuzhiyun CTRL0_SPDIF_CLK_SEL,
110*4882a593Smuzhiyun FIELD_PREP(CTRL0_SPDIF_SEL, mux) |
111*4882a593Smuzhiyun FIELD_PREP(CTRL0_SPDIF_CLK_SEL, mux));
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(g12a_tohdmitx_spdif_mux_enum, TOHDMITX_CTRL0,
119*4882a593Smuzhiyun CTRL0_SPDIF_SEL_SHIFT,
120*4882a593Smuzhiyun g12a_tohdmitx_spdif_mux_texts);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun static const struct snd_kcontrol_new g12a_tohdmitx_spdif_mux =
123*4882a593Smuzhiyun SOC_DAPM_ENUM_EXT("SPDIF Source", g12a_tohdmitx_spdif_mux_enum,
124*4882a593Smuzhiyun snd_soc_dapm_get_enum_double,
125*4882a593Smuzhiyun g12a_tohdmitx_spdif_mux_put_enum);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun static const struct snd_kcontrol_new g12a_tohdmitx_out_enable =
128*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("Switch", TOHDMITX_CTRL0,
129*4882a593Smuzhiyun CTRL0_ENABLE_SHIFT, 1, 0);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static const struct snd_soc_dapm_widget g12a_tohdmitx_widgets[] = {
132*4882a593Smuzhiyun SND_SOC_DAPM_MUX("I2S SRC", SND_SOC_NOPM, 0, 0,
133*4882a593Smuzhiyun &g12a_tohdmitx_i2s_mux),
134*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("I2S OUT EN", SND_SOC_NOPM, 0, 0,
135*4882a593Smuzhiyun &g12a_tohdmitx_out_enable),
136*4882a593Smuzhiyun SND_SOC_DAPM_MUX("SPDIF SRC", SND_SOC_NOPM, 0, 0,
137*4882a593Smuzhiyun &g12a_tohdmitx_spdif_mux),
138*4882a593Smuzhiyun SND_SOC_DAPM_SWITCH("SPDIF OUT EN", SND_SOC_NOPM, 0, 0,
139*4882a593Smuzhiyun &g12a_tohdmitx_out_enable),
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static const struct snd_soc_dai_ops g12a_tohdmitx_input_ops = {
143*4882a593Smuzhiyun .hw_params = meson_codec_glue_input_hw_params,
144*4882a593Smuzhiyun .set_fmt = meson_codec_glue_input_set_fmt,
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static const struct snd_soc_dai_ops g12a_tohdmitx_output_ops = {
148*4882a593Smuzhiyun .startup = meson_codec_glue_output_startup,
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun #define TOHDMITX_SPDIF_FORMATS \
152*4882a593Smuzhiyun (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
153*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun #define TOHDMITX_I2S_FORMATS \
156*4882a593Smuzhiyun (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
157*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
158*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE)
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #define TOHDMITX_STREAM(xname, xsuffix, xfmt, xchmax) \
161*4882a593Smuzhiyun { \
162*4882a593Smuzhiyun .stream_name = xname " " xsuffix, \
163*4882a593Smuzhiyun .channels_min = 1, \
164*4882a593Smuzhiyun .channels_max = (xchmax), \
165*4882a593Smuzhiyun .rate_min = 8000, \
166*4882a593Smuzhiyun .rate_max = 192000, \
167*4882a593Smuzhiyun .formats = (xfmt), \
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun #define TOHDMITX_IN(xname, xid, xfmt, xchmax) { \
171*4882a593Smuzhiyun .name = xname, \
172*4882a593Smuzhiyun .id = (xid), \
173*4882a593Smuzhiyun .playback = TOHDMITX_STREAM(xname, "Playback", xfmt, xchmax), \
174*4882a593Smuzhiyun .ops = &g12a_tohdmitx_input_ops, \
175*4882a593Smuzhiyun .probe = meson_codec_glue_input_dai_probe, \
176*4882a593Smuzhiyun .remove = meson_codec_glue_input_dai_remove, \
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun #define TOHDMITX_OUT(xname, xid, xfmt, xchmax) { \
180*4882a593Smuzhiyun .name = xname, \
181*4882a593Smuzhiyun .id = (xid), \
182*4882a593Smuzhiyun .capture = TOHDMITX_STREAM(xname, "Capture", xfmt, xchmax), \
183*4882a593Smuzhiyun .ops = &g12a_tohdmitx_output_ops, \
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static struct snd_soc_dai_driver g12a_tohdmitx_dai_drv[] = {
187*4882a593Smuzhiyun TOHDMITX_IN("I2S IN A", TOHDMITX_I2S_IN_A,
188*4882a593Smuzhiyun TOHDMITX_I2S_FORMATS, 8),
189*4882a593Smuzhiyun TOHDMITX_IN("I2S IN B", TOHDMITX_I2S_IN_B,
190*4882a593Smuzhiyun TOHDMITX_I2S_FORMATS, 8),
191*4882a593Smuzhiyun TOHDMITX_IN("I2S IN C", TOHDMITX_I2S_IN_C,
192*4882a593Smuzhiyun TOHDMITX_I2S_FORMATS, 8),
193*4882a593Smuzhiyun TOHDMITX_OUT("I2S OUT", TOHDMITX_I2S_OUT,
194*4882a593Smuzhiyun TOHDMITX_I2S_FORMATS, 8),
195*4882a593Smuzhiyun TOHDMITX_IN("SPDIF IN A", TOHDMITX_SPDIF_IN_A,
196*4882a593Smuzhiyun TOHDMITX_SPDIF_FORMATS, 2),
197*4882a593Smuzhiyun TOHDMITX_IN("SPDIF IN B", TOHDMITX_SPDIF_IN_B,
198*4882a593Smuzhiyun TOHDMITX_SPDIF_FORMATS, 2),
199*4882a593Smuzhiyun TOHDMITX_OUT("SPDIF OUT", TOHDMITX_SPDIF_OUT,
200*4882a593Smuzhiyun TOHDMITX_SPDIF_FORMATS, 2),
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun
g12a_tohdmi_component_probe(struct snd_soc_component * c)203*4882a593Smuzhiyun static int g12a_tohdmi_component_probe(struct snd_soc_component *c)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun /* Initialize the static clock parameters */
206*4882a593Smuzhiyun return snd_soc_component_write(c, TOHDMITX_CTRL0,
207*4882a593Smuzhiyun CTRL0_I2S_BLK_CAP_INV | CTRL0_SPDIF_CLK_CAP_INV);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun static const struct snd_soc_dapm_route g12a_tohdmitx_routes[] = {
211*4882a593Smuzhiyun { "I2S SRC", "I2S A", "I2S IN A Playback" },
212*4882a593Smuzhiyun { "I2S SRC", "I2S B", "I2S IN B Playback" },
213*4882a593Smuzhiyun { "I2S SRC", "I2S C", "I2S IN C Playback" },
214*4882a593Smuzhiyun { "I2S OUT EN", "Switch", "I2S SRC" },
215*4882a593Smuzhiyun { "I2S OUT Capture", NULL, "I2S OUT EN" },
216*4882a593Smuzhiyun { "SPDIF SRC", "SPDIF A", "SPDIF IN A Playback" },
217*4882a593Smuzhiyun { "SPDIF SRC", "SPDIF B", "SPDIF IN B Playback" },
218*4882a593Smuzhiyun { "SPDIF OUT EN", "Switch", "SPDIF SRC" },
219*4882a593Smuzhiyun { "SPDIF OUT Capture", NULL, "SPDIF OUT EN" },
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun static const struct snd_soc_component_driver g12a_tohdmitx_component_drv = {
223*4882a593Smuzhiyun .probe = g12a_tohdmi_component_probe,
224*4882a593Smuzhiyun .dapm_widgets = g12a_tohdmitx_widgets,
225*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(g12a_tohdmitx_widgets),
226*4882a593Smuzhiyun .dapm_routes = g12a_tohdmitx_routes,
227*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(g12a_tohdmitx_routes),
228*4882a593Smuzhiyun .endianness = 1,
229*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun static const struct regmap_config g12a_tohdmitx_regmap_cfg = {
233*4882a593Smuzhiyun .reg_bits = 32,
234*4882a593Smuzhiyun .val_bits = 32,
235*4882a593Smuzhiyun .reg_stride = 4,
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun static const struct of_device_id g12a_tohdmitx_of_match[] = {
239*4882a593Smuzhiyun { .compatible = "amlogic,g12a-tohdmitx", },
240*4882a593Smuzhiyun {}
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, g12a_tohdmitx_of_match);
243*4882a593Smuzhiyun
g12a_tohdmitx_probe(struct platform_device * pdev)244*4882a593Smuzhiyun static int g12a_tohdmitx_probe(struct platform_device *pdev)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun struct device *dev = &pdev->dev;
247*4882a593Smuzhiyun void __iomem *regs;
248*4882a593Smuzhiyun struct regmap *map;
249*4882a593Smuzhiyun int ret;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun ret = device_reset(dev);
252*4882a593Smuzhiyun if (ret)
253*4882a593Smuzhiyun return ret;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun regs = devm_platform_ioremap_resource(pdev, 0);
256*4882a593Smuzhiyun if (IS_ERR(regs))
257*4882a593Smuzhiyun return PTR_ERR(regs);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun map = devm_regmap_init_mmio(dev, regs, &g12a_tohdmitx_regmap_cfg);
260*4882a593Smuzhiyun if (IS_ERR(map)) {
261*4882a593Smuzhiyun dev_err(dev, "failed to init regmap: %ld\n",
262*4882a593Smuzhiyun PTR_ERR(map));
263*4882a593Smuzhiyun return PTR_ERR(map);
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun return devm_snd_soc_register_component(dev,
267*4882a593Smuzhiyun &g12a_tohdmitx_component_drv, g12a_tohdmitx_dai_drv,
268*4882a593Smuzhiyun ARRAY_SIZE(g12a_tohdmitx_dai_drv));
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun static struct platform_driver g12a_tohdmitx_pdrv = {
272*4882a593Smuzhiyun .driver = {
273*4882a593Smuzhiyun .name = G12A_TOHDMITX_DRV_NAME,
274*4882a593Smuzhiyun .of_match_table = g12a_tohdmitx_of_match,
275*4882a593Smuzhiyun },
276*4882a593Smuzhiyun .probe = g12a_tohdmitx_probe,
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun module_platform_driver(g12a_tohdmitx_pdrv);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
281*4882a593Smuzhiyun MODULE_DESCRIPTION("Amlogic G12a To HDMI Tx Control Codec Driver");
282*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
283