1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 BayLibre, SAS. 4*4882a593Smuzhiyun * Author: Jerome Brunet <jbrunet@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _MESON_AXG_FIFO_H 8*4882a593Smuzhiyun #define _MESON_AXG_FIFO_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct clk; 11*4882a593Smuzhiyun struct platform_device; 12*4882a593Smuzhiyun struct reg_field; 13*4882a593Smuzhiyun struct regmap; 14*4882a593Smuzhiyun struct regmap_field; 15*4882a593Smuzhiyun struct reset_control; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct snd_soc_component_driver; 18*4882a593Smuzhiyun struct snd_soc_dai; 19*4882a593Smuzhiyun struct snd_soc_dai_driver; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct snd_soc_pcm_runtime; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define AXG_FIFO_CH_MAX 128 24*4882a593Smuzhiyun #define AXG_FIFO_RATES (SNDRV_PCM_RATE_5512 | \ 25*4882a593Smuzhiyun SNDRV_PCM_RATE_8000_192000) 26*4882a593Smuzhiyun #define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 27*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S16_LE | \ 28*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S20_LE | \ 29*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | \ 30*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE | \ 31*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define AXG_FIFO_BURST 8 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define FIFO_INT_ADDR_FINISH BIT(0) 36*4882a593Smuzhiyun #define FIFO_INT_ADDR_INT BIT(1) 37*4882a593Smuzhiyun #define FIFO_INT_COUNT_REPEAT BIT(2) 38*4882a593Smuzhiyun #define FIFO_INT_COUNT_ONCE BIT(3) 39*4882a593Smuzhiyun #define FIFO_INT_FIFO_ZERO BIT(4) 40*4882a593Smuzhiyun #define FIFO_INT_FIFO_DEPTH BIT(5) 41*4882a593Smuzhiyun #define FIFO_INT_MASK GENMASK(7, 0) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define FIFO_CTRL0 0x00 44*4882a593Smuzhiyun #define CTRL0_DMA_EN BIT(31) 45*4882a593Smuzhiyun #define CTRL0_INT_EN(x) ((x) << 16) 46*4882a593Smuzhiyun #define CTRL0_SEL_MASK GENMASK(2, 0) 47*4882a593Smuzhiyun #define CTRL0_SEL_SHIFT 0 48*4882a593Smuzhiyun #define FIFO_CTRL1 0x04 49*4882a593Smuzhiyun #define CTRL1_INT_CLR(x) ((x) << 0) 50*4882a593Smuzhiyun #define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8) 51*4882a593Smuzhiyun #define CTRL1_STATUS2_SEL(x) ((x) << 8) 52*4882a593Smuzhiyun #define STATUS2_SEL_DDR_READ 0 53*4882a593Smuzhiyun #define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24) 54*4882a593Smuzhiyun #define CTRL1_FRDDR_DEPTH(x) ((x) << 24) 55*4882a593Smuzhiyun #define FIFO_START_ADDR 0x08 56*4882a593Smuzhiyun #define FIFO_FINISH_ADDR 0x0c 57*4882a593Smuzhiyun #define FIFO_INT_ADDR 0x10 58*4882a593Smuzhiyun #define FIFO_STATUS1 0x14 59*4882a593Smuzhiyun #define STATUS1_INT_STS(x) ((x) << 0) 60*4882a593Smuzhiyun #define FIFO_STATUS2 0x18 61*4882a593Smuzhiyun #define FIFO_INIT_ADDR 0x24 62*4882a593Smuzhiyun #define FIFO_CTRL2 0x28 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct axg_fifo { 65*4882a593Smuzhiyun struct regmap *map; 66*4882a593Smuzhiyun struct clk *pclk; 67*4882a593Smuzhiyun struct reset_control *arb; 68*4882a593Smuzhiyun struct regmap_field *field_threshold; 69*4882a593Smuzhiyun unsigned int depth; 70*4882a593Smuzhiyun int irq; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct axg_fifo_match_data { 74*4882a593Smuzhiyun const struct snd_soc_component_driver *component_drv; 75*4882a593Smuzhiyun struct snd_soc_dai_driver *dai_drv; 76*4882a593Smuzhiyun struct reg_field field_threshold; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun int axg_fifo_pcm_open(struct snd_soc_component *component, 80*4882a593Smuzhiyun struct snd_pcm_substream *ss); 81*4882a593Smuzhiyun int axg_fifo_pcm_close(struct snd_soc_component *component, 82*4882a593Smuzhiyun struct snd_pcm_substream *ss); 83*4882a593Smuzhiyun int axg_fifo_pcm_hw_params(struct snd_soc_component *component, 84*4882a593Smuzhiyun struct snd_pcm_substream *ss, 85*4882a593Smuzhiyun struct snd_pcm_hw_params *params); 86*4882a593Smuzhiyun int g12a_fifo_pcm_hw_params(struct snd_soc_component *component, 87*4882a593Smuzhiyun struct snd_pcm_substream *ss, 88*4882a593Smuzhiyun struct snd_pcm_hw_params *params); 89*4882a593Smuzhiyun int axg_fifo_pcm_hw_free(struct snd_soc_component *component, 90*4882a593Smuzhiyun struct snd_pcm_substream *ss); 91*4882a593Smuzhiyun snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component, 92*4882a593Smuzhiyun struct snd_pcm_substream *ss); 93*4882a593Smuzhiyun int axg_fifo_pcm_trigger(struct snd_soc_component *component, 94*4882a593Smuzhiyun struct snd_pcm_substream *ss, int cmd); 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type); 97*4882a593Smuzhiyun int axg_fifo_probe(struct platform_device *pdev); 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif /* _MESON_AXG_FIFO_H */ 100