1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 BayLibre, SAS. 4*4882a593Smuzhiyun * Author: Jerome Brunet <jbrunet@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _MESON_AIU_H 8*4882a593Smuzhiyun #define _MESON_AIU_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct clk; 11*4882a593Smuzhiyun struct clk_bulk_data; 12*4882a593Smuzhiyun struct device; 13*4882a593Smuzhiyun struct of_phandle_args; 14*4882a593Smuzhiyun struct snd_soc_dai; 15*4882a593Smuzhiyun struct snd_soc_dai_ops; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun enum aiu_clk_ids { 18*4882a593Smuzhiyun PCLK = 0, 19*4882a593Smuzhiyun AOCLK, 20*4882a593Smuzhiyun MCLK, 21*4882a593Smuzhiyun MIXER 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct aiu_interface { 25*4882a593Smuzhiyun struct clk_bulk_data *clks; 26*4882a593Smuzhiyun unsigned int clk_num; 27*4882a593Smuzhiyun int irq; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct aiu_platform_data { 31*4882a593Smuzhiyun bool has_acodec; 32*4882a593Smuzhiyun bool has_clk_ctrl_more_i2s_div; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct aiu { 36*4882a593Smuzhiyun struct clk *pclk; 37*4882a593Smuzhiyun struct clk *spdif_mclk; 38*4882a593Smuzhiyun struct aiu_interface i2s; 39*4882a593Smuzhiyun struct aiu_interface spdif; 40*4882a593Smuzhiyun const struct aiu_platform_data *platform; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define AIU_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 44*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S20_LE | \ 45*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun int aiu_of_xlate_dai_name(struct snd_soc_component *component, 48*4882a593Smuzhiyun struct of_phandle_args *args, 49*4882a593Smuzhiyun const char **dai_name, 50*4882a593Smuzhiyun unsigned int component_id); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun int aiu_hdmi_ctrl_register_component(struct device *dev); 53*4882a593Smuzhiyun int aiu_acodec_ctrl_register_component(struct device *dev); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai); 56*4882a593Smuzhiyun int aiu_fifo_spdif_dai_probe(struct snd_soc_dai *dai); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun extern const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops; 59*4882a593Smuzhiyun extern const struct snd_soc_dai_ops aiu_fifo_spdif_dai_ops; 60*4882a593Smuzhiyun extern const struct snd_soc_dai_ops aiu_encoder_i2s_dai_ops; 61*4882a593Smuzhiyun extern const struct snd_soc_dai_ops aiu_encoder_spdif_dai_ops; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define AIU_IEC958_BPF 0x000 64*4882a593Smuzhiyun #define AIU_958_MISC 0x010 65*4882a593Smuzhiyun #define AIU_IEC958_DCU_FF_CTRL 0x01c 66*4882a593Smuzhiyun #define AIU_958_CHSTAT_L0 0x020 67*4882a593Smuzhiyun #define AIU_958_CHSTAT_L1 0x024 68*4882a593Smuzhiyun #define AIU_958_CTRL 0x028 69*4882a593Smuzhiyun #define AIU_I2S_SOURCE_DESC 0x034 70*4882a593Smuzhiyun #define AIU_I2S_DAC_CFG 0x040 71*4882a593Smuzhiyun #define AIU_I2S_SYNC 0x044 72*4882a593Smuzhiyun #define AIU_I2S_MISC 0x048 73*4882a593Smuzhiyun #define AIU_RST_SOFT 0x054 74*4882a593Smuzhiyun #define AIU_CLK_CTRL 0x058 75*4882a593Smuzhiyun #define AIU_CLK_CTRL_MORE 0x064 76*4882a593Smuzhiyun #define AIU_CODEC_DAC_LRCLK_CTRL 0x0a0 77*4882a593Smuzhiyun #define AIU_HDMI_CLK_DATA_CTRL 0x0a8 78*4882a593Smuzhiyun #define AIU_ACODEC_CTRL 0x0b0 79*4882a593Smuzhiyun #define AIU_958_CHSTAT_R0 0x0c0 80*4882a593Smuzhiyun #define AIU_958_CHSTAT_R1 0x0c4 81*4882a593Smuzhiyun #define AIU_MEM_I2S_START 0x180 82*4882a593Smuzhiyun #define AIU_MEM_I2S_MASKS 0x18c 83*4882a593Smuzhiyun #define AIU_MEM_I2S_CONTROL 0x190 84*4882a593Smuzhiyun #define AIU_MEM_IEC958_START 0x194 85*4882a593Smuzhiyun #define AIU_MEM_IEC958_CONTROL 0x1a4 86*4882a593Smuzhiyun #define AIU_MEM_I2S_BUF_CNTL 0x1d8 87*4882a593Smuzhiyun #define AIU_MEM_IEC958_BUF_CNTL 0x1fc 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif /* _MESON_AIU_H */ 90