1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Mediatek MT8183 audio driver interconnection definition 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 6*4882a593Smuzhiyun * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _MT8183_INTERCONNECTION_H_ 10*4882a593Smuzhiyun #define _MT8183_INTERCONNECTION_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define I_I2S0_CH1 0 13*4882a593Smuzhiyun #define I_I2S0_CH2 1 14*4882a593Smuzhiyun #define I_ADDA_UL_CH1 3 15*4882a593Smuzhiyun #define I_ADDA_UL_CH2 4 16*4882a593Smuzhiyun #define I_DL1_CH1 5 17*4882a593Smuzhiyun #define I_DL1_CH2 6 18*4882a593Smuzhiyun #define I_DL2_CH1 7 19*4882a593Smuzhiyun #define I_DL2_CH2 8 20*4882a593Smuzhiyun #define I_PCM_1_CAP_CH1 9 21*4882a593Smuzhiyun #define I_GAIN1_OUT_CH1 10 22*4882a593Smuzhiyun #define I_GAIN1_OUT_CH2 11 23*4882a593Smuzhiyun #define I_GAIN2_OUT_CH1 12 24*4882a593Smuzhiyun #define I_GAIN2_OUT_CH2 13 25*4882a593Smuzhiyun #define I_PCM_2_CAP_CH1 14 26*4882a593Smuzhiyun #define I_PCM_2_CAP_CH2 21 27*4882a593Smuzhiyun #define I_PCM_1_CAP_CH2 22 28*4882a593Smuzhiyun #define I_DL3_CH1 23 29*4882a593Smuzhiyun #define I_DL3_CH2 24 30*4882a593Smuzhiyun #define I_I2S2_CH1 25 31*4882a593Smuzhiyun #define I_I2S2_CH2 26 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif 34