xref: /OK3568_Linux_fs/kernel/sound/soc/mediatek/mt8183/mt8183-afe-common.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * mt8183-afe-common.h  --  Mediatek 8183 audio driver definitions
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2018 MediaTek Inc.
6*4882a593Smuzhiyun  * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #ifndef _MT_8183_AFE_COMMON_H_
10*4882a593Smuzhiyun #define _MT_8183_AFE_COMMON_H_
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <sound/soc.h>
13*4882a593Smuzhiyun #include <linux/list.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include "../common/mtk-base-afe.h"
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun enum {
18*4882a593Smuzhiyun 	MT8183_MEMIF_DL1,
19*4882a593Smuzhiyun 	MT8183_MEMIF_DL2,
20*4882a593Smuzhiyun 	MT8183_MEMIF_DL3,
21*4882a593Smuzhiyun 	MT8183_MEMIF_VUL12,
22*4882a593Smuzhiyun 	MT8183_MEMIF_VUL2,
23*4882a593Smuzhiyun 	MT8183_MEMIF_AWB,
24*4882a593Smuzhiyun 	MT8183_MEMIF_AWB2,
25*4882a593Smuzhiyun 	MT8183_MEMIF_MOD_DAI,
26*4882a593Smuzhiyun 	MT8183_MEMIF_HDMI,
27*4882a593Smuzhiyun 	MT8183_MEMIF_NUM,
28*4882a593Smuzhiyun 	MT8183_DAI_ADDA = MT8183_MEMIF_NUM,
29*4882a593Smuzhiyun 	MT8183_DAI_PCM_1,
30*4882a593Smuzhiyun 	MT8183_DAI_PCM_2,
31*4882a593Smuzhiyun 	MT8183_DAI_I2S_0,
32*4882a593Smuzhiyun 	MT8183_DAI_I2S_1,
33*4882a593Smuzhiyun 	MT8183_DAI_I2S_2,
34*4882a593Smuzhiyun 	MT8183_DAI_I2S_3,
35*4882a593Smuzhiyun 	MT8183_DAI_I2S_5,
36*4882a593Smuzhiyun 	MT8183_DAI_TDM,
37*4882a593Smuzhiyun 	MT8183_DAI_HOSTLESS_LPBK,
38*4882a593Smuzhiyun 	MT8183_DAI_HOSTLESS_SPEECH,
39*4882a593Smuzhiyun 	MT8183_DAI_NUM,
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun enum {
43*4882a593Smuzhiyun 	MT8183_IRQ_0,
44*4882a593Smuzhiyun 	MT8183_IRQ_1,
45*4882a593Smuzhiyun 	MT8183_IRQ_2,
46*4882a593Smuzhiyun 	MT8183_IRQ_3,
47*4882a593Smuzhiyun 	MT8183_IRQ_4,
48*4882a593Smuzhiyun 	MT8183_IRQ_5,
49*4882a593Smuzhiyun 	MT8183_IRQ_6,
50*4882a593Smuzhiyun 	MT8183_IRQ_7,
51*4882a593Smuzhiyun 	MT8183_IRQ_8,	/* hw bundle to TDM */
52*4882a593Smuzhiyun 	MT8183_IRQ_11,
53*4882a593Smuzhiyun 	MT8183_IRQ_12,
54*4882a593Smuzhiyun 	MT8183_IRQ_NUM,
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun enum {
58*4882a593Smuzhiyun 	MT8183_MTKAIF_PROTOCOL_1 = 0,
59*4882a593Smuzhiyun 	MT8183_MTKAIF_PROTOCOL_2,
60*4882a593Smuzhiyun 	MT8183_MTKAIF_PROTOCOL_2_CLK_P2,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /* MCLK */
64*4882a593Smuzhiyun enum {
65*4882a593Smuzhiyun 	MT8183_I2S0_MCK = 0,
66*4882a593Smuzhiyun 	MT8183_I2S1_MCK,
67*4882a593Smuzhiyun 	MT8183_I2S2_MCK,
68*4882a593Smuzhiyun 	MT8183_I2S3_MCK,
69*4882a593Smuzhiyun 	MT8183_I2S4_MCK,
70*4882a593Smuzhiyun 	MT8183_I2S4_BCK,
71*4882a593Smuzhiyun 	MT8183_I2S5_MCK,
72*4882a593Smuzhiyun 	MT8183_MCK_NUM,
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun struct clk;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun struct mt8183_afe_private {
78*4882a593Smuzhiyun 	struct clk **clk;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	int pm_runtime_bypass_reg_ctl;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	/* dai */
83*4882a593Smuzhiyun 	void *dai_priv[MT8183_DAI_NUM];
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/* adda */
86*4882a593Smuzhiyun 	int mtkaif_protocol;
87*4882a593Smuzhiyun 	int mtkaif_calibration_ok;
88*4882a593Smuzhiyun 	int mtkaif_chosen_phase[4];
89*4882a593Smuzhiyun 	int mtkaif_phase_cycle[4];
90*4882a593Smuzhiyun 	int mtkaif_calibration_num_phase;
91*4882a593Smuzhiyun 	int mtkaif_dmic;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	/* mck */
94*4882a593Smuzhiyun 	int mck_rate[MT8183_MCK_NUM];
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun unsigned int mt8183_general_rate_transform(struct device *dev,
98*4882a593Smuzhiyun 					   unsigned int rate);
99*4882a593Smuzhiyun unsigned int mt8183_rate_transform(struct device *dev,
100*4882a593Smuzhiyun 				   unsigned int rate, int aud_blk);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun /* dai register */
103*4882a593Smuzhiyun int mt8183_dai_adda_register(struct mtk_base_afe *afe);
104*4882a593Smuzhiyun int mt8183_dai_pcm_register(struct mtk_base_afe *afe);
105*4882a593Smuzhiyun int mt8183_dai_i2s_register(struct mtk_base_afe *afe);
106*4882a593Smuzhiyun int mt8183_dai_tdm_register(struct mtk_base_afe *afe);
107*4882a593Smuzhiyun int mt8183_dai_hostless_register(struct mtk_base_afe *afe);
108*4882a593Smuzhiyun #endif
109