1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mt8183-afe-clk.h -- Mediatek 8183 afe clock ctrl definition 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 6*4882a593Smuzhiyun * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _MT8183_AFE_CLK_H_ 10*4882a593Smuzhiyun #define _MT8183_AFE_CLK_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* APLL */ 13*4882a593Smuzhiyun #define APLL1_W_NAME "APLL1" 14*4882a593Smuzhiyun #define APLL2_W_NAME "APLL2" 15*4882a593Smuzhiyun enum { 16*4882a593Smuzhiyun MT8183_APLL1 = 0, 17*4882a593Smuzhiyun MT8183_APLL2, 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct mtk_base_afe; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun int mt8183_init_clock(struct mtk_base_afe *afe); 23*4882a593Smuzhiyun int mt8183_afe_enable_clock(struct mtk_base_afe *afe); 24*4882a593Smuzhiyun int mt8183_afe_disable_clock(struct mtk_base_afe *afe); 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun int mt8183_apll1_enable(struct mtk_base_afe *afe); 27*4882a593Smuzhiyun void mt8183_apll1_disable(struct mtk_base_afe *afe); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun int mt8183_apll2_enable(struct mtk_base_afe *afe); 30*4882a593Smuzhiyun void mt8183_apll2_disable(struct mtk_base_afe *afe); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll); 33*4882a593Smuzhiyun int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate); 34*4882a593Smuzhiyun int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate); 37*4882a593Smuzhiyun void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id); 38*4882a593Smuzhiyun #endif 39