1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // MediaTek ALSA SoC Audio DAI ADDA Control
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2018 MediaTek Inc.
6*4882a593Smuzhiyun // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/regmap.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include "mt6797-afe-common.h"
11*4882a593Smuzhiyun #include "mt6797-interconnection.h"
12*4882a593Smuzhiyun #include "mt6797-reg.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun enum {
15*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_8K = 0,
16*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_11K = 1,
17*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_12K = 2,
18*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_16K = 3,
19*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_22K = 4,
20*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_24K = 5,
21*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_32K = 6,
22*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_44K = 7,
23*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_48K = 8,
24*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_96K = 9,
25*4882a593Smuzhiyun MTK_AFE_ADDA_DL_RATE_192K = 10,
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun enum {
29*4882a593Smuzhiyun MTK_AFE_ADDA_UL_RATE_8K = 0,
30*4882a593Smuzhiyun MTK_AFE_ADDA_UL_RATE_16K = 1,
31*4882a593Smuzhiyun MTK_AFE_ADDA_UL_RATE_32K = 2,
32*4882a593Smuzhiyun MTK_AFE_ADDA_UL_RATE_48K = 3,
33*4882a593Smuzhiyun MTK_AFE_ADDA_UL_RATE_96K = 4,
34*4882a593Smuzhiyun MTK_AFE_ADDA_UL_RATE_192K = 5,
35*4882a593Smuzhiyun MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
adda_dl_rate_transform(struct mtk_base_afe * afe,unsigned int rate)38*4882a593Smuzhiyun static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
39*4882a593Smuzhiyun unsigned int rate)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun switch (rate) {
42*4882a593Smuzhiyun case 8000:
43*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_8K;
44*4882a593Smuzhiyun case 11025:
45*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_11K;
46*4882a593Smuzhiyun case 12000:
47*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_12K;
48*4882a593Smuzhiyun case 16000:
49*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_16K;
50*4882a593Smuzhiyun case 22050:
51*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_22K;
52*4882a593Smuzhiyun case 24000:
53*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_24K;
54*4882a593Smuzhiyun case 32000:
55*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_32K;
56*4882a593Smuzhiyun case 44100:
57*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_44K;
58*4882a593Smuzhiyun case 48000:
59*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_48K;
60*4882a593Smuzhiyun case 96000:
61*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_96K;
62*4882a593Smuzhiyun case 192000:
63*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_192K;
64*4882a593Smuzhiyun default:
65*4882a593Smuzhiyun dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
66*4882a593Smuzhiyun __func__, rate);
67*4882a593Smuzhiyun return MTK_AFE_ADDA_DL_RATE_48K;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
adda_ul_rate_transform(struct mtk_base_afe * afe,unsigned int rate)71*4882a593Smuzhiyun static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
72*4882a593Smuzhiyun unsigned int rate)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun switch (rate) {
75*4882a593Smuzhiyun case 8000:
76*4882a593Smuzhiyun return MTK_AFE_ADDA_UL_RATE_8K;
77*4882a593Smuzhiyun case 16000:
78*4882a593Smuzhiyun return MTK_AFE_ADDA_UL_RATE_16K;
79*4882a593Smuzhiyun case 32000:
80*4882a593Smuzhiyun return MTK_AFE_ADDA_UL_RATE_32K;
81*4882a593Smuzhiyun case 48000:
82*4882a593Smuzhiyun return MTK_AFE_ADDA_UL_RATE_48K;
83*4882a593Smuzhiyun case 96000:
84*4882a593Smuzhiyun return MTK_AFE_ADDA_UL_RATE_96K;
85*4882a593Smuzhiyun case 192000:
86*4882a593Smuzhiyun return MTK_AFE_ADDA_UL_RATE_192K;
87*4882a593Smuzhiyun default:
88*4882a593Smuzhiyun dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
89*4882a593Smuzhiyun __func__, rate);
90*4882a593Smuzhiyun return MTK_AFE_ADDA_UL_RATE_48K;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* dai component */
95*4882a593Smuzhiyun static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
96*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
97*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
98*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
99*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
100*4882a593Smuzhiyun I_ADDA_UL_CH2, 1, 0),
101*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
102*4882a593Smuzhiyun I_ADDA_UL_CH1, 1, 0),
103*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
104*4882a593Smuzhiyun I_PCM_1_CAP_CH1, 1, 0),
105*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
106*4882a593Smuzhiyun I_PCM_2_CAP_CH1, 1, 0),
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
110*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
111*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
112*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
113*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
114*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
115*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
116*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
117*4882a593Smuzhiyun I_ADDA_UL_CH2, 1, 0),
118*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
119*4882a593Smuzhiyun I_ADDA_UL_CH1, 1, 0),
120*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
121*4882a593Smuzhiyun I_PCM_1_CAP_CH1, 1, 0),
122*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
123*4882a593Smuzhiyun I_PCM_2_CAP_CH1, 1, 0),
124*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
125*4882a593Smuzhiyun I_PCM_1_CAP_CH2, 1, 0),
126*4882a593Smuzhiyun SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
127*4882a593Smuzhiyun I_PCM_2_CAP_CH2, 1, 0),
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun
mtk_adda_ul_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)130*4882a593Smuzhiyun static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
131*4882a593Smuzhiyun struct snd_kcontrol *kcontrol,
132*4882a593Smuzhiyun int event)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
135*4882a593Smuzhiyun struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
138*4882a593Smuzhiyun __func__, w->name, event);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun switch (event) {
141*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
142*4882a593Smuzhiyun /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
143*4882a593Smuzhiyun usleep_range(125, 135);
144*4882a593Smuzhiyun break;
145*4882a593Smuzhiyun default:
146*4882a593Smuzhiyun break;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun return 0;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun enum {
153*4882a593Smuzhiyun SUPPLY_SEQ_AUD_TOP_PDN,
154*4882a593Smuzhiyun SUPPLY_SEQ_ADDA_AFE_ON,
155*4882a593Smuzhiyun SUPPLY_SEQ_ADDA_DL_ON,
156*4882a593Smuzhiyun SUPPLY_SEQ_ADDA_UL_ON,
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
160*4882a593Smuzhiyun /* adda */
161*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
162*4882a593Smuzhiyun mtk_adda_dl_ch1_mix,
163*4882a593Smuzhiyun ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
164*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
165*4882a593Smuzhiyun mtk_adda_dl_ch2_mix,
166*4882a593Smuzhiyun ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
169*4882a593Smuzhiyun AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
170*4882a593Smuzhiyun NULL, 0),
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
173*4882a593Smuzhiyun AFE_ADDA_DL_SRC2_CON0,
174*4882a593Smuzhiyun DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
175*4882a593Smuzhiyun NULL, 0),
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
178*4882a593Smuzhiyun AFE_ADDA_UL_SRC_CON0,
179*4882a593Smuzhiyun UL_SRC_ON_TMP_CTL_SFT, 0,
180*4882a593Smuzhiyun mtk_adda_ul_event,
181*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMD),
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("aud_dac_clk", SUPPLY_SEQ_AUD_TOP_PDN,
184*4882a593Smuzhiyun AUDIO_TOP_CON0, PDN_DAC_SFT, 1,
185*4882a593Smuzhiyun NULL, 0),
186*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("aud_dac_predis_clk", SUPPLY_SEQ_AUD_TOP_PDN,
187*4882a593Smuzhiyun AUDIO_TOP_CON0, PDN_DAC_PREDIS_SFT, 1,
188*4882a593Smuzhiyun NULL, 0),
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY_S("aud_adc_clk", SUPPLY_SEQ_AUD_TOP_PDN,
191*4882a593Smuzhiyun AUDIO_TOP_CON0, PDN_ADC_SFT, 1,
192*4882a593Smuzhiyun NULL, 0),
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
198*4882a593Smuzhiyun /* playback */
199*4882a593Smuzhiyun {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
200*4882a593Smuzhiyun {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
201*4882a593Smuzhiyun {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
204*4882a593Smuzhiyun {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
205*4882a593Smuzhiyun {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
208*4882a593Smuzhiyun {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
209*4882a593Smuzhiyun {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun {"ADDA Playback", NULL, "ADDA_DL_CH1"},
212*4882a593Smuzhiyun {"ADDA Playback", NULL, "ADDA_DL_CH2"},
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /* adda enable */
215*4882a593Smuzhiyun {"ADDA Playback", NULL, "ADDA Enable"},
216*4882a593Smuzhiyun {"ADDA Playback", NULL, "ADDA Playback Enable"},
217*4882a593Smuzhiyun {"ADDA Capture", NULL, "ADDA Enable"},
218*4882a593Smuzhiyun {"ADDA Capture", NULL, "ADDA Capture Enable"},
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun /* clk */
221*4882a593Smuzhiyun {"ADDA Playback", NULL, "mtkaif_26m_clk"},
222*4882a593Smuzhiyun {"ADDA Playback", NULL, "aud_dac_clk"},
223*4882a593Smuzhiyun {"ADDA Playback", NULL, "aud_dac_predis_clk"},
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun {"ADDA Capture", NULL, "mtkaif_26m_clk"},
226*4882a593Smuzhiyun {"ADDA Capture", NULL, "aud_adc_clk"},
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun /* dai ops */
mtk_dai_adda_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)230*4882a593Smuzhiyun static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
231*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
232*4882a593Smuzhiyun struct snd_soc_dai *dai)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
235*4882a593Smuzhiyun unsigned int rate = params_rate(params);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
238*4882a593Smuzhiyun __func__, dai->id, substream->stream, rate);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
241*4882a593Smuzhiyun unsigned int dl_src2_con0 = 0;
242*4882a593Smuzhiyun unsigned int dl_src2_con1 = 0;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /* clean predistortion */
245*4882a593Smuzhiyun regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
246*4882a593Smuzhiyun regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* set input sampling rate */
249*4882a593Smuzhiyun dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /* set output mode */
252*4882a593Smuzhiyun switch (rate) {
253*4882a593Smuzhiyun case 192000:
254*4882a593Smuzhiyun dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
255*4882a593Smuzhiyun dl_src2_con0 |= 1 << 14;
256*4882a593Smuzhiyun break;
257*4882a593Smuzhiyun case 96000:
258*4882a593Smuzhiyun dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
259*4882a593Smuzhiyun dl_src2_con0 |= 1 << 14;
260*4882a593Smuzhiyun break;
261*4882a593Smuzhiyun default:
262*4882a593Smuzhiyun dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
263*4882a593Smuzhiyun break;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /* turn off mute function */
267*4882a593Smuzhiyun dl_src2_con0 |= (0x03 << 11);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /* set voice input data if input sample rate is 8k or 16k */
270*4882a593Smuzhiyun if (rate == 8000 || rate == 16000)
271*4882a593Smuzhiyun dl_src2_con0 |= 0x01 << 5;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun if (rate < 96000) {
274*4882a593Smuzhiyun /* SA suggest apply -0.3db to audio/speech path */
275*4882a593Smuzhiyun dl_src2_con1 = 0xf74f0000;
276*4882a593Smuzhiyun } else {
277*4882a593Smuzhiyun /* SA suggest apply -0.3db to audio/speech path
278*4882a593Smuzhiyun * with DL gain set to half,
279*4882a593Smuzhiyun * 0xFFFF = 0dB -> 0x8000 = 0dB when 96k, 192k
280*4882a593Smuzhiyun */
281*4882a593Smuzhiyun dl_src2_con1 = 0x7ba70000;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun /* turn on down-link gain */
285*4882a593Smuzhiyun dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
288*4882a593Smuzhiyun regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
289*4882a593Smuzhiyun } else {
290*4882a593Smuzhiyun unsigned int voice_mode = 0;
291*4882a593Smuzhiyun unsigned int ul_src_con0 = 0; /* default value */
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /* Using Internal ADC */
294*4882a593Smuzhiyun regmap_update_bits(afe->regmap,
295*4882a593Smuzhiyun AFE_ADDA_TOP_CON0,
296*4882a593Smuzhiyun 0x1 << 0,
297*4882a593Smuzhiyun 0x0 << 0);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun voice_mode = adda_ul_rate_transform(afe, rate);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /* up8x txif sat on */
304*4882a593Smuzhiyun regmap_write(afe->regmap, AFE_ADDA_NEWIF_CFG0, 0x03F87201);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun if (rate >= 96000) { /* hires */
307*4882a593Smuzhiyun /* use hires format [1 0 23] */
308*4882a593Smuzhiyun regmap_update_bits(afe->regmap,
309*4882a593Smuzhiyun AFE_ADDA_NEWIF_CFG0,
310*4882a593Smuzhiyun 0x1 << 5,
311*4882a593Smuzhiyun 0x1 << 5);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun regmap_update_bits(afe->regmap,
314*4882a593Smuzhiyun AFE_ADDA_NEWIF_CFG2,
315*4882a593Smuzhiyun 0xf << 28,
316*4882a593Smuzhiyun voice_mode << 28);
317*4882a593Smuzhiyun } else { /* normal 8~48k */
318*4882a593Smuzhiyun /* use fixed 260k anc path */
319*4882a593Smuzhiyun regmap_update_bits(afe->regmap,
320*4882a593Smuzhiyun AFE_ADDA_NEWIF_CFG2,
321*4882a593Smuzhiyun 0xf << 28,
322*4882a593Smuzhiyun 8 << 28);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /* ul_use_cic_out */
325*4882a593Smuzhiyun ul_src_con0 |= 0x1 << 20;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun regmap_update_bits(afe->regmap,
329*4882a593Smuzhiyun AFE_ADDA_NEWIF_CFG2,
330*4882a593Smuzhiyun 0xf << 28,
331*4882a593Smuzhiyun 8 << 28);
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun regmap_update_bits(afe->regmap,
334*4882a593Smuzhiyun AFE_ADDA_UL_SRC_CON0,
335*4882a593Smuzhiyun 0xfffffffe,
336*4882a593Smuzhiyun ul_src_con0);
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun return 0;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
343*4882a593Smuzhiyun .hw_params = mtk_dai_adda_hw_params,
344*4882a593Smuzhiyun };
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun /* dai driver */
347*4882a593Smuzhiyun #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
348*4882a593Smuzhiyun SNDRV_PCM_RATE_96000 |\
349*4882a593Smuzhiyun SNDRV_PCM_RATE_192000)
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
352*4882a593Smuzhiyun SNDRV_PCM_RATE_16000 |\
353*4882a593Smuzhiyun SNDRV_PCM_RATE_32000 |\
354*4882a593Smuzhiyun SNDRV_PCM_RATE_48000 |\
355*4882a593Smuzhiyun SNDRV_PCM_RATE_96000 |\
356*4882a593Smuzhiyun SNDRV_PCM_RATE_192000)
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
359*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE |\
360*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE)
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun .name = "ADDA",
365*4882a593Smuzhiyun .id = MT6797_DAI_ADDA,
366*4882a593Smuzhiyun .playback = {
367*4882a593Smuzhiyun .stream_name = "ADDA Playback",
368*4882a593Smuzhiyun .channels_min = 1,
369*4882a593Smuzhiyun .channels_max = 2,
370*4882a593Smuzhiyun .rates = MTK_ADDA_PLAYBACK_RATES,
371*4882a593Smuzhiyun .formats = MTK_ADDA_FORMATS,
372*4882a593Smuzhiyun },
373*4882a593Smuzhiyun .capture = {
374*4882a593Smuzhiyun .stream_name = "ADDA Capture",
375*4882a593Smuzhiyun .channels_min = 1,
376*4882a593Smuzhiyun .channels_max = 2,
377*4882a593Smuzhiyun .rates = MTK_ADDA_CAPTURE_RATES,
378*4882a593Smuzhiyun .formats = MTK_ADDA_FORMATS,
379*4882a593Smuzhiyun },
380*4882a593Smuzhiyun .ops = &mtk_dai_adda_ops,
381*4882a593Smuzhiyun },
382*4882a593Smuzhiyun };
383*4882a593Smuzhiyun
mt6797_dai_adda_register(struct mtk_base_afe * afe)384*4882a593Smuzhiyun int mt6797_dai_adda_register(struct mtk_base_afe *afe)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun struct mtk_base_afe_dai *dai;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
389*4882a593Smuzhiyun if (!dai)
390*4882a593Smuzhiyun return -ENOMEM;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun list_add(&dai->list, &afe->sub_dais);
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun dai->dai_drivers = mtk_dai_adda_driver;
395*4882a593Smuzhiyun dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun dai->dapm_widgets = mtk_dai_adda_widgets;
398*4882a593Smuzhiyun dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
399*4882a593Smuzhiyun dai->dapm_routes = mtk_dai_adda_routes;
400*4882a593Smuzhiyun dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
401*4882a593Smuzhiyun return 0;
402*4882a593Smuzhiyun }
403