1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // mt6797-afe-clk.c -- Mediatek 6797 afe clock ctrl
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2018 MediaTek Inc.
6*4882a593Smuzhiyun // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "mt6797-afe-common.h"
11*4882a593Smuzhiyun #include "mt6797-afe-clk.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun enum {
14*4882a593Smuzhiyun CLK_INFRA_SYS_AUD,
15*4882a593Smuzhiyun CLK_INFRA_SYS_AUD_26M,
16*4882a593Smuzhiyun CLK_TOP_MUX_AUD,
17*4882a593Smuzhiyun CLK_TOP_MUX_AUD_BUS,
18*4882a593Smuzhiyun CLK_TOP_SYSPLL3_D4,
19*4882a593Smuzhiyun CLK_TOP_SYSPLL1_D4,
20*4882a593Smuzhiyun CLK_CLK26M,
21*4882a593Smuzhiyun CLK_NUM
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static const char *aud_clks[CLK_NUM] = {
25*4882a593Smuzhiyun [CLK_INFRA_SYS_AUD] = "infra_sys_audio_clk",
26*4882a593Smuzhiyun [CLK_INFRA_SYS_AUD_26M] = "infra_sys_audio_26m",
27*4882a593Smuzhiyun [CLK_TOP_MUX_AUD] = "top_mux_audio",
28*4882a593Smuzhiyun [CLK_TOP_MUX_AUD_BUS] = "top_mux_aud_intbus",
29*4882a593Smuzhiyun [CLK_TOP_SYSPLL3_D4] = "top_sys_pll3_d4",
30*4882a593Smuzhiyun [CLK_TOP_SYSPLL1_D4] = "top_sys_pll1_d4",
31*4882a593Smuzhiyun [CLK_CLK26M] = "top_clk26m_clk",
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
mt6797_init_clock(struct mtk_base_afe * afe)34*4882a593Smuzhiyun int mt6797_init_clock(struct mtk_base_afe *afe)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun struct mt6797_afe_private *afe_priv = afe->platform_priv;
37*4882a593Smuzhiyun int i;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
40*4882a593Smuzhiyun GFP_KERNEL);
41*4882a593Smuzhiyun if (!afe_priv->clk)
42*4882a593Smuzhiyun return -ENOMEM;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun for (i = 0; i < CLK_NUM; i++) {
45*4882a593Smuzhiyun afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
46*4882a593Smuzhiyun if (IS_ERR(afe_priv->clk[i])) {
47*4882a593Smuzhiyun dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
48*4882a593Smuzhiyun __func__, aud_clks[i],
49*4882a593Smuzhiyun PTR_ERR(afe_priv->clk[i]));
50*4882a593Smuzhiyun return PTR_ERR(afe_priv->clk[i]);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
mt6797_afe_enable_clock(struct mtk_base_afe * afe)57*4882a593Smuzhiyun int mt6797_afe_enable_clock(struct mtk_base_afe *afe)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct mt6797_afe_private *afe_priv = afe->platform_priv;
60*4882a593Smuzhiyun int ret;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD]);
63*4882a593Smuzhiyun if (ret) {
64*4882a593Smuzhiyun dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
65*4882a593Smuzhiyun __func__, aud_clks[CLK_INFRA_SYS_AUD], ret);
66*4882a593Smuzhiyun goto CLK_INFRA_SYS_AUDIO_ERR;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
70*4882a593Smuzhiyun if (ret) {
71*4882a593Smuzhiyun dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
72*4882a593Smuzhiyun __func__, aud_clks[CLK_INFRA_SYS_AUD_26M], ret);
73*4882a593Smuzhiyun goto CLK_INFRA_SYS_AUD_26M_ERR;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD]);
77*4882a593Smuzhiyun if (ret) {
78*4882a593Smuzhiyun dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
79*4882a593Smuzhiyun __func__, aud_clks[CLK_TOP_MUX_AUD], ret);
80*4882a593Smuzhiyun goto CLK_MUX_AUDIO_ERR;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD],
84*4882a593Smuzhiyun afe_priv->clk[CLK_CLK26M]);
85*4882a593Smuzhiyun if (ret) {
86*4882a593Smuzhiyun dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
87*4882a593Smuzhiyun __func__, aud_clks[CLK_TOP_MUX_AUD],
88*4882a593Smuzhiyun aud_clks[CLK_CLK26M], ret);
89*4882a593Smuzhiyun goto CLK_MUX_AUDIO_ERR;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
93*4882a593Smuzhiyun if (ret) {
94*4882a593Smuzhiyun dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
95*4882a593Smuzhiyun __func__, aud_clks[CLK_TOP_MUX_AUD_BUS], ret);
96*4882a593Smuzhiyun goto CLK_MUX_AUDIO_INTBUS_ERR;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return ret;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun CLK_MUX_AUDIO_INTBUS_ERR:
102*4882a593Smuzhiyun clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
103*4882a593Smuzhiyun CLK_MUX_AUDIO_ERR:
104*4882a593Smuzhiyun clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);
105*4882a593Smuzhiyun CLK_INFRA_SYS_AUD_26M_ERR:
106*4882a593Smuzhiyun clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
107*4882a593Smuzhiyun CLK_INFRA_SYS_AUDIO_ERR:
108*4882a593Smuzhiyun clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return 0;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
mt6797_afe_disable_clock(struct mtk_base_afe * afe)113*4882a593Smuzhiyun int mt6797_afe_disable_clock(struct mtk_base_afe *afe)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct mt6797_afe_private *afe_priv = afe->platform_priv;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
118*4882a593Smuzhiyun clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);
119*4882a593Smuzhiyun clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
120*4882a593Smuzhiyun clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return 0;
123*4882a593Smuzhiyun }
124