1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mt2701-reg.h -- Mediatek 2701 audio driver reg definition 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2016 MediaTek Inc. 6*4882a593Smuzhiyun * Author: Garlic Tseng <garlic.tseng@mediatek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _MT2701_REG_H_ 10*4882a593Smuzhiyun #define _MT2701_REG_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define AUDIO_TOP_CON0 0x0000 13*4882a593Smuzhiyun #define AUDIO_TOP_CON4 0x0010 14*4882a593Smuzhiyun #define AUDIO_TOP_CON5 0x0014 15*4882a593Smuzhiyun #define AFE_DAIBT_CON0 0x001c 16*4882a593Smuzhiyun #define AFE_MRGIF_CON 0x003c 17*4882a593Smuzhiyun #define ASMI_TIMING_CON1 0x0100 18*4882a593Smuzhiyun #define ASMO_TIMING_CON1 0x0104 19*4882a593Smuzhiyun #define PWR1_ASM_CON1 0x0108 20*4882a593Smuzhiyun #define ASYS_TOP_CON 0x0600 21*4882a593Smuzhiyun #define ASYS_I2SIN1_CON 0x0604 22*4882a593Smuzhiyun #define ASYS_I2SIN2_CON 0x0608 23*4882a593Smuzhiyun #define ASYS_I2SIN3_CON 0x060c 24*4882a593Smuzhiyun #define ASYS_I2SIN4_CON 0x0610 25*4882a593Smuzhiyun #define ASYS_I2SIN5_CON 0x0614 26*4882a593Smuzhiyun #define ASYS_I2SO1_CON 0x061C 27*4882a593Smuzhiyun #define ASYS_I2SO2_CON 0x0620 28*4882a593Smuzhiyun #define ASYS_I2SO3_CON 0x0624 29*4882a593Smuzhiyun #define ASYS_I2SO4_CON 0x0628 30*4882a593Smuzhiyun #define ASYS_I2SO5_CON 0x062c 31*4882a593Smuzhiyun #define PWR2_TOP_CON 0x0634 32*4882a593Smuzhiyun #define AFE_CONN0 0x06c0 33*4882a593Smuzhiyun #define AFE_CONN1 0x06c4 34*4882a593Smuzhiyun #define AFE_CONN2 0x06c8 35*4882a593Smuzhiyun #define AFE_CONN3 0x06cc 36*4882a593Smuzhiyun #define AFE_CONN14 0x06f8 37*4882a593Smuzhiyun #define AFE_CONN15 0x06fc 38*4882a593Smuzhiyun #define AFE_CONN16 0x0700 39*4882a593Smuzhiyun #define AFE_CONN17 0x0704 40*4882a593Smuzhiyun #define AFE_CONN18 0x0708 41*4882a593Smuzhiyun #define AFE_CONN19 0x070c 42*4882a593Smuzhiyun #define AFE_CONN20 0x0710 43*4882a593Smuzhiyun #define AFE_CONN21 0x0714 44*4882a593Smuzhiyun #define AFE_CONN22 0x0718 45*4882a593Smuzhiyun #define AFE_CONN23 0x071c 46*4882a593Smuzhiyun #define AFE_CONN24 0x0720 47*4882a593Smuzhiyun #define AFE_CONN41 0x0764 48*4882a593Smuzhiyun #define ASYS_IRQ1_CON 0x0780 49*4882a593Smuzhiyun #define ASYS_IRQ2_CON 0x0784 50*4882a593Smuzhiyun #define ASYS_IRQ3_CON 0x0788 51*4882a593Smuzhiyun #define ASYS_IRQ_CLR 0x07c0 52*4882a593Smuzhiyun #define ASYS_IRQ_STATUS 0x07c4 53*4882a593Smuzhiyun #define PWR2_ASM_CON1 0x1070 54*4882a593Smuzhiyun #define AFE_DAC_CON0 0x1200 55*4882a593Smuzhiyun #define AFE_DAC_CON1 0x1204 56*4882a593Smuzhiyun #define AFE_DAC_CON2 0x1208 57*4882a593Smuzhiyun #define AFE_DAC_CON3 0x120c 58*4882a593Smuzhiyun #define AFE_DAC_CON4 0x1210 59*4882a593Smuzhiyun #define AFE_MEMIF_HD_CON1 0x121c 60*4882a593Smuzhiyun #define AFE_MEMIF_PBUF_SIZE 0x1238 61*4882a593Smuzhiyun #define AFE_MEMIF_HD_CON0 0x123c 62*4882a593Smuzhiyun #define AFE_DL1_BASE 0x1240 63*4882a593Smuzhiyun #define AFE_DL1_CUR 0x1244 64*4882a593Smuzhiyun #define AFE_DL2_BASE 0x1250 65*4882a593Smuzhiyun #define AFE_DL2_CUR 0x1254 66*4882a593Smuzhiyun #define AFE_DL3_BASE 0x1260 67*4882a593Smuzhiyun #define AFE_DL3_CUR 0x1264 68*4882a593Smuzhiyun #define AFE_DL4_BASE 0x1270 69*4882a593Smuzhiyun #define AFE_DL4_CUR 0x1274 70*4882a593Smuzhiyun #define AFE_DL5_BASE 0x1280 71*4882a593Smuzhiyun #define AFE_DL5_CUR 0x1284 72*4882a593Smuzhiyun #define AFE_DLMCH_BASE 0x12a0 73*4882a593Smuzhiyun #define AFE_DLMCH_CUR 0x12a4 74*4882a593Smuzhiyun #define AFE_ARB1_BASE 0x12b0 75*4882a593Smuzhiyun #define AFE_ARB1_CUR 0x12b4 76*4882a593Smuzhiyun #define AFE_VUL_BASE 0x1300 77*4882a593Smuzhiyun #define AFE_VUL_CUR 0x130c 78*4882a593Smuzhiyun #define AFE_UL2_BASE 0x1310 79*4882a593Smuzhiyun #define AFE_UL2_END 0x1318 80*4882a593Smuzhiyun #define AFE_UL2_CUR 0x131c 81*4882a593Smuzhiyun #define AFE_UL3_BASE 0x1320 82*4882a593Smuzhiyun #define AFE_UL3_END 0x1328 83*4882a593Smuzhiyun #define AFE_UL3_CUR 0x132c 84*4882a593Smuzhiyun #define AFE_UL4_BASE 0x1330 85*4882a593Smuzhiyun #define AFE_UL4_END 0x1338 86*4882a593Smuzhiyun #define AFE_UL4_CUR 0x133c 87*4882a593Smuzhiyun #define AFE_UL5_BASE 0x1340 88*4882a593Smuzhiyun #define AFE_UL5_END 0x1348 89*4882a593Smuzhiyun #define AFE_UL5_CUR 0x134c 90*4882a593Smuzhiyun #define AFE_DAI_BASE 0x1370 91*4882a593Smuzhiyun #define AFE_DAI_CUR 0x137c 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* AFE_DAIBT_CON0 (0x001c) */ 94*4882a593Smuzhiyun #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0) 95*4882a593Smuzhiyun #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1) 96*4882a593Smuzhiyun #define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3) 97*4882a593Smuzhiyun #define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9) 98*4882a593Smuzhiyun #define AFE_DAIBT_CON0_MRG_USE (0x1 << 12) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* PWR1_ASM_CON1 (0x0108) */ 101*4882a593Smuzhiyun #define PWR1_ASM_CON1_INIT_VAL (0x492) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* AFE_MRGIF_CON (0x003c) */ 104*4882a593Smuzhiyun #define AFE_MRGIF_CON_MRG_EN (0x1 << 0) 105*4882a593Smuzhiyun #define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16) 106*4882a593Smuzhiyun #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20) 107*4882a593Smuzhiyun #define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* ASYS_TOP_CON (0x0600) */ 110*4882a593Smuzhiyun #define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* PWR2_ASM_CON1 (0x1070) */ 113*4882a593Smuzhiyun #define PWR2_ASM_CON1_INIT_VAL (0x492492) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* AFE_DAC_CON0 (0x1200) */ 116*4882a593Smuzhiyun #define AFE_DAC_CON0_AFE_ON (0x1 << 0) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* AFE_MEMIF_PBUF_SIZE (0x1238) */ 119*4882a593Smuzhiyun #define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29) 120*4882a593Smuzhiyun #define AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE (0x0 << 29) 121*4882a593Smuzhiyun #define AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE (0x1 << 29) 122*4882a593Smuzhiyun #define DLMCH_BIT_WIDTH_MASK (0x1 << 28) 123*4882a593Smuzhiyun #define AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK (0xf << 24) 124*4882a593Smuzhiyun #define AFE_MEMIF_PBUF_SIZE_DLM_CH(x) ((x) << 24) 125*4882a593Smuzhiyun #define AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK (0x3 << 12) 126*4882a593Smuzhiyun #define AFE_MEMIF_PBUF_SIZE_DLM_32BYTES (0x1 << 12) 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* I2S in/out register bit control */ 129*4882a593Smuzhiyun #define ASYS_I2S_CON_FS (0x1f << 8) 130*4882a593Smuzhiyun #define ASYS_I2S_CON_FS_SET(x) ((x) << 8) 131*4882a593Smuzhiyun #define ASYS_I2S_CON_RESET (0x1 << 30) 132*4882a593Smuzhiyun #define ASYS_I2S_CON_I2S_EN (0x1 << 0) 133*4882a593Smuzhiyun #define ASYS_I2S_CON_ONE_HEART_MODE (0x1 << 16) 134*4882a593Smuzhiyun #define ASYS_I2S_CON_I2S_COUPLE_MODE (0x1 << 17) 135*4882a593Smuzhiyun /* 0:EIAJ 1:I2S */ 136*4882a593Smuzhiyun #define ASYS_I2S_CON_I2S_MODE (0x1 << 3) 137*4882a593Smuzhiyun #define ASYS_I2S_CON_WIDE_MODE (0x1 << 1) 138*4882a593Smuzhiyun #define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1) 139*4882a593Smuzhiyun #define ASYS_I2S_IN_PHASE_FIX (0x1 << 31) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif 142