1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mt2701-afe-common.h -- Mediatek 2701 audio driver definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2016 MediaTek Inc. 6*4882a593Smuzhiyun * Author: Garlic Tseng <garlic.tseng@mediatek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _MT_2701_AFE_COMMON_H_ 10*4882a593Smuzhiyun #define _MT_2701_AFE_COMMON_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <sound/soc.h> 13*4882a593Smuzhiyun #include <linux/clk.h> 14*4882a593Smuzhiyun #include <linux/regmap.h> 15*4882a593Smuzhiyun #include "mt2701-reg.h" 16*4882a593Smuzhiyun #include "../common/mtk-base-afe.h" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MT2701_PLL_DOMAIN_0_RATE 98304000 19*4882a593Smuzhiyun #define MT2701_PLL_DOMAIN_1_RATE 90316800 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun enum { 22*4882a593Smuzhiyun MT2701_MEMIF_DL1, 23*4882a593Smuzhiyun MT2701_MEMIF_DL2, 24*4882a593Smuzhiyun MT2701_MEMIF_DL3, 25*4882a593Smuzhiyun MT2701_MEMIF_DL4, 26*4882a593Smuzhiyun MT2701_MEMIF_DL5, 27*4882a593Smuzhiyun MT2701_MEMIF_DL_SINGLE_NUM, 28*4882a593Smuzhiyun MT2701_MEMIF_DLM = MT2701_MEMIF_DL_SINGLE_NUM, 29*4882a593Smuzhiyun MT2701_MEMIF_UL1, 30*4882a593Smuzhiyun MT2701_MEMIF_UL2, 31*4882a593Smuzhiyun MT2701_MEMIF_UL3, 32*4882a593Smuzhiyun MT2701_MEMIF_UL4, 33*4882a593Smuzhiyun MT2701_MEMIF_UL5, 34*4882a593Smuzhiyun MT2701_MEMIF_DLBT, 35*4882a593Smuzhiyun MT2701_MEMIF_ULBT, 36*4882a593Smuzhiyun MT2701_MEMIF_NUM, 37*4882a593Smuzhiyun MT2701_IO_I2S = MT2701_MEMIF_NUM, 38*4882a593Smuzhiyun MT2701_IO_2ND_I2S, 39*4882a593Smuzhiyun MT2701_IO_3RD_I2S, 40*4882a593Smuzhiyun MT2701_IO_4TH_I2S, 41*4882a593Smuzhiyun MT2701_IO_5TH_I2S, 42*4882a593Smuzhiyun MT2701_IO_6TH_I2S, 43*4882a593Smuzhiyun MT2701_IO_MRG, 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun enum { 47*4882a593Smuzhiyun MT2701_IRQ_ASYS_IRQ1, 48*4882a593Smuzhiyun MT2701_IRQ_ASYS_IRQ2, 49*4882a593Smuzhiyun MT2701_IRQ_ASYS_IRQ3, 50*4882a593Smuzhiyun MT2701_IRQ_ASYS_END, 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun enum audio_base_clock { 54*4882a593Smuzhiyun MT2701_INFRA_SYS_AUDIO, 55*4882a593Smuzhiyun MT2701_TOP_AUD_MCLK_SRC0, 56*4882a593Smuzhiyun MT2701_TOP_AUD_MCLK_SRC1, 57*4882a593Smuzhiyun MT2701_TOP_AUD_A1SYS, 58*4882a593Smuzhiyun MT2701_TOP_AUD_A2SYS, 59*4882a593Smuzhiyun MT2701_AUDSYS_AFE, 60*4882a593Smuzhiyun MT2701_AUDSYS_AFE_CONN, 61*4882a593Smuzhiyun MT2701_AUDSYS_A1SYS, 62*4882a593Smuzhiyun MT2701_AUDSYS_A2SYS, 63*4882a593Smuzhiyun MT2701_BASE_CLK_NUM, 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct mt2701_i2s_data { 67*4882a593Smuzhiyun int i2s_ctrl_reg; 68*4882a593Smuzhiyun int i2s_asrc_fs_shift; 69*4882a593Smuzhiyun int i2s_asrc_fs_mask; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun struct mt2701_i2s_path { 73*4882a593Smuzhiyun int mclk_rate; 74*4882a593Smuzhiyun int on[MTK_STREAM_NUM]; 75*4882a593Smuzhiyun int occupied[MTK_STREAM_NUM]; 76*4882a593Smuzhiyun const struct mt2701_i2s_data *i2s_data[MTK_STREAM_NUM]; 77*4882a593Smuzhiyun struct clk *hop_ck[MTK_STREAM_NUM]; 78*4882a593Smuzhiyun struct clk *sel_ck; 79*4882a593Smuzhiyun struct clk *div_ck; 80*4882a593Smuzhiyun struct clk *mclk_ck; 81*4882a593Smuzhiyun struct clk *asrco_ck; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun struct mt2701_soc_variants { 85*4882a593Smuzhiyun bool has_one_heart_mode; 86*4882a593Smuzhiyun int i2s_num; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct mt2701_afe_private { 90*4882a593Smuzhiyun struct mt2701_i2s_path *i2s_path; 91*4882a593Smuzhiyun struct clk *base_ck[MT2701_BASE_CLK_NUM]; 92*4882a593Smuzhiyun struct clk *mrgif_ck; 93*4882a593Smuzhiyun bool mrg_enable[MTK_STREAM_NUM]; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun const struct mt2701_soc_variants *soc; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif 99