1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mt2701-afe-clock-ctrl.h -- Mediatek 2701 afe clock ctrl definition 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2016 MediaTek Inc. 6*4882a593Smuzhiyun * Author: Garlic Tseng <garlic.tseng@mediatek.com> 7*4882a593Smuzhiyun * Ryder Lee <ryder.lee@mediatek.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _MT2701_AFE_CLOCK_CTRL_H_ 11*4882a593Smuzhiyun #define _MT2701_AFE_CLOCK_CTRL_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct mtk_base_afe; 14*4882a593Smuzhiyun struct mt2701_i2s_path; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun int mt2701_init_clock(struct mtk_base_afe *afe); 17*4882a593Smuzhiyun int mt2701_afe_enable_clock(struct mtk_base_afe *afe); 18*4882a593Smuzhiyun int mt2701_afe_disable_clock(struct mtk_base_afe *afe); 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, 21*4882a593Smuzhiyun struct mt2701_i2s_path *path, 22*4882a593Smuzhiyun int dir); 23*4882a593Smuzhiyun void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, 24*4882a593Smuzhiyun struct mt2701_i2s_path *path, 25*4882a593Smuzhiyun int dir); 26*4882a593Smuzhiyun int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id); 27*4882a593Smuzhiyun void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe); 30*4882a593Smuzhiyun void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun int mt2701_mclk_configuration(struct mtk_base_afe *afe, int id); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif 35